arm: tegra: p1852: Configure CPU_SOFTRST_CTRL
Bhavesh Parekh [Thu, 4 Oct 2012 09:57:52 +0000 (14:57 +0530)]
CPU_SOFTRST_CTRL register is used during cluster-switching. It tells the
delays for un-clamping and reset in term of sclk cycle

On P1852, we are running SCLK at 334MHz so we can't use the
reset value of this register.
Currently configuring the value with high number till we get proper
value from qual team

Bug 1051967
Bug 1010500

Reviewed-on: http://git-master/r/141524
(cherry picked from commit ac86e1d722cb4efd152bc3c335be7ce91205c88c)
Change-Id: I768b68c694543f7a3f2a6c4435e9829aeaeaa51c
Signed-off-by: Nitin Agrawal <nitina@nvidia.com>
Reviewed-on: http://git-master/r/146496
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

arch/arm/mach-tegra/board-p1852-power.c

index ac2f747..022ac22 100644 (file)
 #include "pm.h"
 #include "wakeups-t3.h"
 
+#define CPU_SOFTRST_CTRL               0x380
+
+static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
+
+#define clk_writel(value, reg) \
+       __raw_writel(value, (u32)reg_clk_base + (reg))
 
 static struct tegra_suspend_platform_data p1852_suspend_data = {
        /* FIXME: This value needs to come from SysEng */
@@ -31,8 +37,11 @@ static struct tegra_suspend_platform_data p1852_suspend_data = {
        .cpu_lp2_min_residency = 2000,
 };
 
+
 int __init p1852_suspend_init(void)
 {
+       /* FIXME Get correct value from sys-eng */
+       clk_writel(0x8040, CPU_SOFTRST_CTRL);
        tegra_init_suspend(&p1852_suspend_data);
        return 0;
 }