crypto: tegra-aes: set vde clock to max in _probe
Varun Wadekar [Mon, 24 Jan 2011 10:00:19 +0000 (15:00 +0530)]
Original-Change-Id: I41ba8dfc193b346eda522eadfb0f9035f4d838f8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/22160
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R8351adfba377ede436f101194551e8091aa5528b

drivers/crypto/tegra-aes.c

index 1256587..028a220 100644 (file)
@@ -229,14 +229,6 @@ static int aes_hw_init(struct tegra_aes_dev *dd)
                return ret;
        }
 
-       ret = clk_set_rate(dd->iclk, 240000000);
-       if (ret) {
-               dev_err(dd->dev, "%s: iclk set_rate fail(%d)\n", __func__, ret);
-               clk_disable(dd->iclk);
-               clk_disable(dd->pclk);
-               return ret;
-       }
-
        aes_writel(dd, 0x33, INT_ENB);
        return ret;
 }
@@ -1001,6 +993,12 @@ static int tegra_aes_probe(struct platform_device *pdev)
                goto out;
        }
 
+       err = clk_set_rate(dd->iclk, ULONG_MAX);
+       if (err) {
+               dev_err(dd->dev, "iclk set_rate fail(%d)\n", err);
+               goto out;
+       }
+
        /*
         * the foll contiguous memory is allocated as follows -
         * - hardware key table