video: tegra: dsi: Refine the DSI clock calculation.
Kevin Huang [Wed, 18 Jan 2012 00:28:55 +0000 (16:28 -0800)]
Reviewed-on: http://git-master/r/76406

Change-Id: I6e5b37a88d6be4ba2cc81417fe3eadfd129bc899
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77306
Reviewed-by: Automatic_Commit_Validation_User

drivers/video/tegra/dc/dc.c
drivers/video/tegra/dc/dc_priv.h
drivers/video/tegra/dc/dsi.c

index 45962ba..bdd0a02 100644 (file)
@@ -1460,7 +1460,7 @@ void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
                        }
                }
 
-               rate = dc->mode.pclk * 2;
+               rate = dc->mode.pclk * dc->shift_clk_div * 2;
                if (rate != clk_get_rate(base_clk))
                        clk_set_rate(base_clk, rate);
 
@@ -2737,6 +2737,7 @@ static int tegra_dc_probe(struct nvhost_device *ndev)
 
        dc->clk = clk;
        dc->emc_clk = emc_clk;
+       dc->shift_clk_div = 1;
 
        dc->base_res = base_res;
        dc->base = base;
index 2a01a83..30b5ea9 100644 (file)
@@ -82,6 +82,7 @@ struct tegra_dc {
        struct clk                      *emc_clk;
        int                             emc_clk_rate;
        int                             new_emc_clk_rate;
+       u32                             shift_clk_div;
 
        bool                            connected;
        bool                            enabled;
index 8290275..2c511ef 100644 (file)
@@ -946,21 +946,23 @@ static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
 {
        u32 rm;
 
+       /* Round up to MHz */
        rm = clk % 1000;
        if (rm != 0)
                clk -= rm;
 
-       dc->mode.pclk = clk*1000;
+       /* Set up pixel clock */
+       dc->shift_clk_div = dsi->shift_clk_div;
+       dc->mode.pclk = (clk * 1000) / dsi->shift_clk_div;
+
+       /* Enable DSI clock */
        tegra_dc_setup_clk(dc, dsi->dsi_clk);
-       if (dsi->clk_ref == true)
-               clk_disable(dsi->dsi_clk);
-       else
+       if (!dsi->clk_ref) {
                dsi->clk_ref = true;
-       clk_enable(dsi->dsi_clk);
-       tegra_periph_reset_deassert(dsi->dsi_clk);
-
+               clk_enable(dsi->dsi_clk);
+               tegra_periph_reset_deassert(dsi->dsi_clk);
+       }
        dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
-
        dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
 }