[arm]: tegra:cardhu Creating board files
Laxman Dewangan [Wed, 22 Dec 2010 10:02:30 +0000 (15:02 +0530)]
Creating initial board files and config files for cardhu.

Original-Change-Id: I84b78bdf2363137bcf2c7dd4c556a23b1dd73bd0
Reviewed-on: http://git-master/r/12193
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I0ccc2fd52a56d43b69252cb110287da9197d1193

Rebase-Id: R0e4f04b5ae83693b536842eb7d15857333d7432a

arch/arm/mach-tegra/Kconfig
arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/board-cardhu-panel.c [new file with mode: 0644]
arch/arm/mach-tegra/board-cardhu-pinmux.c [new file with mode: 0644]
arch/arm/mach-tegra/board-cardhu-power.c [new file with mode: 0644]
arch/arm/mach-tegra/board-cardhu-sdhci.c [new file with mode: 0644]
arch/arm/mach-tegra/board-cardhu-sensors.c [new file with mode: 0644]
arch/arm/mach-tegra/board-cardhu.c [new file with mode: 0644]
arch/arm/mach-tegra/board-cardhu.h [new file with mode: 0644]

index 81b8e19..02b3de6 100644 (file)
@@ -140,6 +140,11 @@ config MACH_VENTANA
 
 # Cardhu
 
+config MACH_CARDHU
+       bool "Cardhu board"
+       help
+         Support for NVIDIA Cardhu development platform
+
 # Enterprise
 
 choice
index 1a077d9..617a32c 100644 (file)
@@ -132,5 +132,11 @@ obj-$(CONFIG_MACH_VENTANA)              += board-ventana-panel.o
 # Whistler
 
 # Cardhu
+obj-${CONFIG_MACH_CARDHU}               += board-cardhu.o
+obj-${CONFIG_MACH_CARDHU}               += board-cardhu-panel.o
+obj-${CONFIG_MACH_CARDHU}               += board-cardhu-pinmux.o
+obj-${CONFIG_MACH_CARDHU}               += board-cardhu-power.o
+obj-${CONFIG_MACH_CARDHU}               += board-cardhu-sdhci.o
+obj-${CONFIG_MACH_CARDHU}               += board-cardhu-sensors.o
 
 # Enterprise
diff --git a/arch/arm/mach-tegra/board-cardhu-panel.c b/arch/arm/mach-tegra/board-cardhu-panel.c
new file mode 100644 (file)
index 0000000..864ba5f
--- /dev/null
@@ -0,0 +1,252 @@
+/*
+ * arch/arm/mach-tegra/board-cardhu-panel.c
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/resource.h>
+#include <asm/mach-types.h>
+#include <linux/platform_device.h>
+#include <linux/pwm_backlight.h>
+#include <mach/nvhost.h>
+#include <mach/nvmap.h>
+#include <mach/irqs.h>
+#include <mach/iomap.h>
+#include <mach/dc.h>
+#include <mach/fb.h>
+
+#include "devices.h"
+#include "gpio-names.h"
+
+#define PMC_SCRATCH20  0xa0
+
+#define cardhu_lvds_shutdown   TEGRA_GPIO_PB2
+
+static int cardhu_panel_enable(void)
+{
+       static struct regulator *reg = NULL;
+
+       if (reg == NULL) {
+               reg = regulator_get(NULL, "avdd_lvds");
+               if (WARN_ON(IS_ERR(reg)))
+                       pr_err("%s: couldn't get regulator avdd_lvds: %ld\n",
+                              __func__, PTR_ERR(reg));
+               else
+                       regulator_enable(reg);
+       }
+
+       gpio_set_value(cardhu_lvds_shutdown, 1);
+       return 0;
+}
+
+static int cardhu_panel_disable(void)
+{
+       gpio_set_value(cardhu_lvds_shutdown, 0);
+       return 0;
+}
+
+static struct resource cardhu_disp1_resources[] = {
+       {
+               .name   = "irq",
+               .start  = INT_DISPLAY_GENERAL,
+               .end    = INT_DISPLAY_GENERAL,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               .name   = "regs",
+               .start  = TEGRA_DISPLAY_BASE,
+               .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "fbmem",
+               .start  = 0,    /* Filled in by fbmem_set() */
+               .end    = 0,    /* Filled in by fbmem_set() */
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct tegra_dc_mode cardhu_panel_modes[] = {
+       {
+               .pclk = 18000000,
+               .h_ref_to_sync = 8,
+               .v_ref_to_sync = 2,
+               .h_sync_width = 4,
+               .v_sync_width = 1,
+               .h_back_porch = 20,
+               .v_back_porch = 7,
+               .h_active = 480,
+               .v_active = 640,
+               .h_front_porch = 8,
+               .v_front_porch = 8,
+       },
+};
+
+static struct tegra_fb_data cardhu_fb_data = {
+       .win            = 0,
+       .xres           = 1366,
+       .yres           = 768,
+       .bits_per_pixel = 16,
+};
+
+static struct tegra_dc_out cardhu_disp1_out = {
+       .type           = TEGRA_DC_OUT_RGB,
+
+       .align          = TEGRA_DC_ALIGN_MSB,
+       .order          = TEGRA_DC_ORDER_RED_BLUE,
+
+       .modes          = cardhu_panel_modes,
+       .n_modes        = ARRAY_SIZE(cardhu_panel_modes),
+
+       .enable         = cardhu_panel_enable,
+       .disable        = cardhu_panel_disable,
+};
+
+static struct tegra_dc_platform_data cardhu_disp1_pdata = {
+       .flags          = TEGRA_DC_FLAG_ENABLED,
+       .default_out    = &cardhu_disp1_out,
+       .fb             = &cardhu_fb_data,
+};
+
+static struct nvhost_device cardhu_disp1_device = {
+       .name           = "tegradc",
+       .id             = 0,
+       .resource       = cardhu_disp1_resources,
+       .num_resources  = ARRAY_SIZE(cardhu_disp1_resources),
+       .dev = {
+               .platform_data = &cardhu_disp1_pdata,
+       },
+};
+
+static struct nvmap_platform_carveout cardhu_carveouts[] = {
+       [0] = {
+               .name           = "iram",
+               .usage_mask     = NVMAP_HEAP_CARVEOUT_IRAM,
+               .base           = TEGRA_IRAM_BASE,
+               .size           = TEGRA_IRAM_SIZE,
+               .buddy_size     = 0, /* no buddy allocation for IRAM */
+       },
+       [1] = {
+               .name           = "generic-0",
+               .usage_mask     = NVMAP_HEAP_CARVEOUT_GENERIC,
+               .base           = 0,    /* Filled in by carveout_set() */
+               .size           = 0,    /* Filled in by carveout_set() */
+               .buddy_size     = SZ_32K,
+       },
+};
+
+static struct nvmap_platform_data cardhu_nvmap_data = {
+       .carveouts      = cardhu_carveouts,
+       .nr_carveouts   = ARRAY_SIZE(cardhu_carveouts),
+};
+
+static struct platform_device cardhu_nvmap_device = {
+       .name   = "tegra-nvmap",
+       .id     = -1,
+       .dev    = {
+               .platform_data = &cardhu_nvmap_data,
+       },
+};
+
+static struct platform_device *cardhu_gfx_devices[] __initdata = {
+       &cardhu_nvmap_device,
+       &tegra_grhost_device,
+};
+
+
+static inline u32 pmc_readl(unsigned long offset)
+{
+       return readl(IO_TO_VIRT(TEGRA_PMC_BASE + offset));
+}
+
+static void fbmem_set(struct resource *res, int num_res,
+                               u32 start, resource_size_t size)
+{
+       int i;
+       for (i = 0; i < num_res ; i++) {
+               if (!strcmp(res[i].name, "fbmem")) {
+                       res[i].start = start;
+                       res[i].end = start + size - 1;
+                       return;
+               }
+       }
+       /* Didn't find a framebuffer memory resource */
+       BUG();
+}
+
+static void carveout_set(struct nvmap_platform_carveout *res, int num_res,
+                               u32 base, resource_size_t size)
+{
+       int i;
+       for (i = 0; i < num_res ; i++) {
+               if (!strcmp(res[i].name, "generic-0")) {
+                       res[i].base = base;
+                       res[i].size = size;
+                       return;
+               }
+       }
+       /* Didn't find a carveout memory resource */
+       BUG();
+}
+
+int __init cardhu_panel_init(void)
+{
+       int err;
+       u32 odm_data = pmc_readl(PMC_SCRATCH20);
+
+       /* !!!FIXME!!!  HAVE TO USE HARD-CODED FRAME BUFFER AND CARVEOUT
+                       ADDRESSES FOR NOW -- BUG 769986 */
+       switch (odm_data & 0x70000000) {
+       case 0x10000000:
+               /* 256MB LPDDR2 */
+               fbmem_set(cardhu_disp1_resources,
+                               ARRAY_SIZE(cardhu_disp1_resources),
+                               0x8E010000,
+                               0x0012C3C0);
+               carveout_set(cardhu_carveouts,
+                               ARRAY_SIZE(cardhu_carveouts),
+                               0x8EC00000, /* 256MB mem - 32MB carveout + 0xC00000 ?*/
+                               SZ_32M - 0xC00000);
+               break;
+       case 0x40000000:
+               /* 1GB DDR3 -- NOTE: The bootloader cannot map more than 512MB
+                  of physical memory. Therefore, the frame buffer and carveout
+                  must be completely below the 512MB boundary. */
+               fbmem_set(cardhu_disp1_resources,
+                               ARRAY_SIZE(cardhu_disp1_resources),
+                               0x9E010000,
+                               0x0012C3C0);
+               carveout_set(cardhu_carveouts,
+                               ARRAY_SIZE(cardhu_carveouts),
+                               0x9EC00000, /* 512MB mem - 32MB carveout + 0xC00000 ?*/
+                               SZ_32M - 0xC00000);
+               break;
+       default:
+               BUG();
+       }
+
+       err = platform_add_devices(cardhu_gfx_devices,
+                                  ARRAY_SIZE(cardhu_gfx_devices));
+
+       if (!err)
+               err = nvhost_device_register(&cardhu_disp1_device);
+
+       return err;
+}
diff --git a/arch/arm/mach-tegra/board-cardhu-pinmux.c b/arch/arm/mach-tegra/board-cardhu-pinmux.c
new file mode 100644 (file)
index 0000000..72bd514
--- /dev/null
@@ -0,0 +1,327 @@
+/*
+ * arch/arm/mach-tegra/board-cardhu-pinmux.c
+ *
+ * Copyright (C) 2010 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <mach/pinmux.h>
+
+#define DEFAULT_DRIVE(_name)                                   \
+       {                                                       \
+               .pingroup = TEGRA_DRIVE_PINGROUP_##_name,       \
+               .hsm = TEGRA_HSM_DISABLE,                       \
+               .schmitt = TEGRA_SCHMITT_ENABLE,                \
+               .drive = TEGRA_DRIVE_DIV_1,                     \
+               .pull_down = TEGRA_PULL_31,                     \
+               .pull_up = TEGRA_PULL_31,                       \
+               .slew_rising = TEGRA_SLEW_SLOWEST,              \
+               .slew_falling = TEGRA_SLEW_SLOWEST,             \
+       }
+/* Setting the drive strength of pins
+ * hsm: Enable High speed mode (ENABLE/DISABLE)
+ * Schimit: Enable/disable schimit (ENABLE/DISABLE)
+ * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
+ * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
+ *                strength code. Value from 0 to 31. 
+ * pullup_drive - drive up (rising edge)  - Driver Output Pull-Up drive
+ *                strength code. Value from 0 to 31.
+ * pulldn_slew -  Driver Output Pull-Up slew control code  - 2bit code
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ * pullup_slew -  Driver Output Pull-Down slew control code - 
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal. 
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ */            
+#define SET_DRIVE(_name, hsm, schitt, drive, pulldn_drive, pullup_drive, pulldn_slew, pullup_slew) \
+       {                                                       \
+               .pingroup = TEGRA_DRIVE_PINGROUP_##_name,       \
+               .hsm = TEGRA_HSM_##hsm,                         \
+               .schmitt = TEGRA_SCHMITT_##scimitt,             \
+               .drive = TEGRA_DRIVE_##drive,                   \
+               .pull_down = TEGRA_PULL_#pulldn_drive,          \
+               .pull_up = TEGRA_PULL_pullup_drive,             \
+               .slew_rising = TEGRA_SLEW_#pulldn_slew,         \
+               .slew_falling = TEGRA_SLEW_#pullup_slew,        \
+       }
+
+// !!!FIXME!!!! POPULATE THIS TABLE
+static __initdata struct tegra_drive_pingroup_config cardhu_drive_pinmux[] = {
+       /* DEFAULT_DRIVE(<pin_group>), */
+       /* SET_DRIVE(ATA, DISABLE, DISABLE, DIV_1, 31, 31, FAST, FAST) */
+};
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io)      \
+       {                                                       \
+               .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
+               .func           = TEGRA_MUX_##_mux,             \
+               .pupd           = TEGRA_PUPD_##_pupd,           \
+               .tristate       = TEGRA_TRI_##_tri,             \
+               .io             = TEGRA_PIN_##_io,              \
+       }
+
+// !!!FIXME!!!! POPULATE THIS TABLE
+static __initdata struct tegra_pingroup_config cardhu_pinmux[] = {
+       DEFAULT_PINMUX(ULPI_DATA0,      UARTA,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA1,      UARTA,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(ULPI_DATA2,      UARTA,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(ULPI_DATA3,      UARTA,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA4,      UARTA,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(ULPI_DATA5,      UARTA,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(ULPI_DATA6,      UARTA,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(ULPI_DATA7,      UARTA,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(ULPI_CLK,        UARTD,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(ULPI_DIR,        UARTD,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(ULPI_NXT,        UARTD,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(ULPI_STP,        UARTD,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(DAP3_FS,         I2S2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP3_DIN,        I2S2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP3_DOUT,       I2S2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP3_SCLK,       I2S2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_CLK,      SDMMC1,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_CMD,      SDMMC1,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT3,     SDMMC1,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT2,     SDMMC1,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT1,     SDMMC1,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT0,     SDMMC1,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PV2,        OWR,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GPIO_PV3,        CLK12,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(CLK2_OUT,        EXTPERIPH2,      NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CLK2_REQ,        DAP,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_PWR1,        DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_PWR2,        DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_SDIN,        DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_SDOUT,       DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_WR_N,        DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_CS0_N,       DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_DC0,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_SCK,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_PWR0,        DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_PCLK,        DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_DE,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_HSYNC,       DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_VSYNC,       DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D0,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D1,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D2,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D3,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D4,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D5,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D6,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D7,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D8,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D9,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D10,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D11,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D12,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D13,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D14,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D15,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D16,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D17,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D18,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D19,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D20,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D21,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D22,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D23,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_CS1_N,       DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_M1,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_DC1,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DDC_SCL,         I2C4,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DDC_SDA,         I2C4,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CRT_HSYNC,       CRT,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(CRT_VSYNC,       CRT,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(VI_D0,           RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(VI_D1,           SDMMC2,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(VI_D2,           SDMMC2,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(VI_D3,           SDMMC2,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(VI_D4,           SDMMC2,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(VI_D5,           SDMMC2,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(VI_D6,           SDMMC2,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(VI_D7,           SDMMC2,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(VI_D8,           SDMMC2,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(VI_D9,           SDMMC2,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(VI_D10,          RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(VI_D11,          RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(VI_PCLK,         SDMMC2,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(VI_MCLK,         VI,              NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(VI_VSYNC,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(VI_HSYNC,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(UART2_RXD,       IRDA,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(UART2_TXD,       IRDA,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(UART2_RTS_N,     GMI,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(UART2_CTS_N,     GMI,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(UART3_TXD,       UARTC,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(UART3_RXD,       UARTC,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(UART3_CTS_N,     UARTC,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(UART3_RTS_N,     UARTC,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GPIO_PU0,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PU1,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PU2,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PU3,        PWM0,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GPIO_PU4,        PWM1,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GPIO_PU5,        PWM2,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GPIO_PU6,        PWM3,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GEN1_I2C_SDA,    I2C1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GEN1_I2C_SCL,    I2C1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP4_FS,         I2S3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP4_DIN,        I2S3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP4_DOUT,       I2S3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP4_SCLK,       I2S3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CLK3_OUT,        EXTPERIPH3,      NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(CLK3_REQ,        DEV3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_WP_N,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_IORDY,       NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_WAIT,        NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_ADV_N,       NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CLK,         NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CS0_N,       NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CS1_N,       NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CS2_N,       NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CS3_N,       NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CS4_N,       NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CS6_N,       NAND_ALT,        NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CS7_N,       NAND_ALT,        NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD0,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD1,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD2,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD3,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD4,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD5,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD6,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD7,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD8,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD9,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD10,        NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD11,        NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD12,        NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD13,        NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD14,        NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD15,        NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_A16,         UARTD,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_A17,         UARTD,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_A18,         UARTD,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_A19,         UARTD,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_WR_N,        NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_OE_N,        NAND,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_DQS,         NAND,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_RST_N,       RSVD3,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GEN2_I2C_SCL,    I2C2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GEN2_I2C_SDA,    I2C2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_CLK,      SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_CMD,      SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT0,     SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT1,     SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT2,     SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT3,     SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT4,     SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT5,     SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT6,     SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT7,     SDMMC4,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_RST_N,    RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CAM_MCLK,        VI,              NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PCC1,       RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB0,       RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CAM_I2C_SCL,     I2C3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CAM_I2C_SDA,     I2C3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB3,       VGP3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB4,       VGP4,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB5,       VGP5,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB6,       VGP6,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB7,       I2S4,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PCC2,       I2S4,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(JTAG_RTCK,       RTCK,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(PWR_I2C_SCL,     I2CPWR,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(PWR_I2C_SDA,     I2CPWR,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW0,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW1,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW2,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW3,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW4,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW5,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW6,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW7,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW8,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW9,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW10,        KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW11,        KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW12,        KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW13,        KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW14,        KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW15,        KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL0,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL1,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL2,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL3,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL4,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL5,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL6,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL7,         KBC,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CLK_32K_OUT,     BLINK,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(SYS_CLK_REQ,     SYSCLK,          NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(OWR,             OWR,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP1_FS,         I2S0,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP1_DIN,        I2S0,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP1_DOUT,       I2S0,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP1_SCLK,       I2S0,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CLK1_REQ,        DAP,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CLK1_OUT,        EXTPERIPH1,      NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPDIF_IN,        SPDIF,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPDIF_OUT,       SPDIF,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(DAP2_FS,         I2S1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP2_DIN,        I2S1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP2_DOUT,       I2S1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP2_SCLK,       I2S1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI2_MOSI,       SPI6,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI2_MISO,       SPI6,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI2_CS0_N,      SPI6,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI2_SCK,        SPI6,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI1_MOSI,       SPI1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI1_SCK,        SPI1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI1_CS0_N,      SPI1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI1_MISO,       SPI1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI2_CS1_N,      SPI3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI2_CS2_N,      SPI3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_CLK,      SDMMC3,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_CMD,      SDMMC3,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT0,     SDMMC3,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT1,     SDMMC3,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT2,     SDMMC3,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT3,     SDMMC3,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT4,     SDMMC3,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT5,     SDMMC3,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT6,     SDMMC3,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT7,     SDMMC3,          NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(PEX_L0_PRSNT_N,  PCIE,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(PEX_L0_RST_N,    PCIE,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(PEX_WAKE_N,      PCIE,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(PEX_L1_PRSNT_N,  PCIE,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(PEX_L1_RST_N,    PCIE,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(PEX_L2_PRSNT_N,  PCIE,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(PEX_L2_RST_N,    PCIE,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(HDMI_CEC,        CEC,             NORMAL,    NORMAL,     INPUT),
+};
+
+void __init cardhu_pinmux_init(void)
+{
+       tegra_pinmux_config_table(cardhu_pinmux, ARRAY_SIZE(cardhu_pinmux));
+       tegra_drive_pinmux_config_table(cardhu_drive_pinmux,
+                                       ARRAY_SIZE(cardhu_drive_pinmux));
+}
diff --git a/arch/arm/mach-tegra/board-cardhu-power.c b/arch/arm/mach-tegra/board-cardhu-power.c
new file mode 100644 (file)
index 0000000..ecee28c
--- /dev/null
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2010 NVIDIA, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+#include <linux/platform_device.h>
+#include <linux/io.h>
+int __init cardhu_regulator_init(void)
+{
+       return 0;
+}
diff --git a/arch/arm/mach-tegra/board-cardhu-sdhci.c b/arch/arm/mach-tegra/board-cardhu-sdhci.c
new file mode 100644 (file)
index 0000000..f437cb3
--- /dev/null
@@ -0,0 +1,133 @@
+/*
+ * arch/arm/mach-tegra/board-harmony-sdhci.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/resource.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/mmc/host.h>
+
+#include <asm/mach-types.h>
+#include <mach/irqs.h>
+#include <mach/iomap.h>
+#include <mach/sdhci.h>
+
+#include "gpio-names.h"
+#include "board.h"
+
+static struct resource sdhci_resource0[] = {
+       [0] = {
+               .start  = INT_SDMMC1,
+               .end    = INT_SDMMC1,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [1] = {
+               .start  = TEGRA_SDMMC1_BASE,
+               .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct resource sdhci_resource2[] = {
+       [0] = {
+               .start  = INT_SDMMC3,
+               .end    = INT_SDMMC3,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [1] = {
+               .start  = TEGRA_SDMMC3_BASE,
+               .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct resource sdhci_resource3[] = {
+       [0] = {
+               .start  = INT_SDMMC4,
+               .end    = INT_SDMMC4,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [1] = {
+               .start  = TEGRA_SDMMC4_BASE,
+               .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
+       .clk_id = NULL,
+       .force_hs = 0,
+       .cd_gpio = -1,
+       .wp_gpio = -1,
+       .power_gpio = -1,
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
+       .clk_id = NULL,
+       .force_hs = 1,
+       .cd_gpio = -1,
+       .wp_gpio = -1,
+       .power_gpio = -1,
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
+       .clk_id = NULL,
+       .force_hs = 0,
+       .cd_gpio = -1,
+       .wp_gpio = -1,
+       .power_gpio = -1,
+};
+
+static struct platform_device tegra_sdhci_device0 = {
+       .name           = "sdhci-tegra",
+       .id             = 0,
+       .resource       = sdhci_resource0,
+       .num_resources  = ARRAY_SIZE(sdhci_resource0),
+       .dev = {
+               .platform_data = &tegra_sdhci_platform_data0,
+       },
+};
+
+static struct platform_device tegra_sdhci_device2 = {
+       .name           = "sdhci-tegra",
+       .id             = 2,
+       .resource       = sdhci_resource2,
+       .num_resources  = ARRAY_SIZE(sdhci_resource2),
+       .dev = {
+               .platform_data = &tegra_sdhci_platform_data2,
+       },
+};
+
+static struct platform_device tegra_sdhci_device3 = {
+       .name           = "sdhci-tegra",
+       .id             = 3,
+       .resource       = sdhci_resource3,
+       .num_resources  = ARRAY_SIZE(sdhci_resource3),
+       .dev = {
+               .platform_data = &tegra_sdhci_platform_data3,
+       },
+};
+
+int __init cardhu_sdhci_init(void)
+{
+       platform_device_register(&tegra_sdhci_device3);
+       platform_device_register(&tegra_sdhci_device2);
+       platform_device_register(&tegra_sdhci_device0);
+       return 0;
+}
diff --git a/arch/arm/mach-tegra/board-cardhu-sensors.c b/arch/arm/mach-tegra/board-cardhu-sensors.c
new file mode 100644 (file)
index 0000000..01b088b
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-tegra/board-cardhu-sensors.c
+ *
+ * Copyright (c) 2010, NVIDIA, All Rights Reserved.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <linux/i2c.h>
+int __init cardhu_sensors_init(void)
+{
+       return 0;
+}
diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c
new file mode 100644 (file)
index 0000000..12b91bc
--- /dev/null
@@ -0,0 +1,402 @@
+/*
+ * arch/arm/mach-tegra/board-cardhu.c
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/serial_8250.h>
+#include <linux/i2c.h>
+#include <linux/i2c/panjit_ts.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/i2c-tegra.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/platform_data/tegra_usb.h>
+#include <mach/clk.h>
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/pinmux.h>
+#include <mach/iomap.h>
+#include <mach/io.h>
+#include <mach/i2s.h>
+#include <mach/audio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/usb_phy.h>
+
+#include "board.h"
+#include "clock.h"
+#include "board-cardhu.h"
+#include "devices.h"
+#include "gpio-names.h"
+#include "fuse.h"
+
+static struct plat_serial8250_port debug_uart_platform_data[] = {
+       {
+               .membase        = IO_ADDRESS(TEGRA_UARTA_BASE),
+               .mapbase        = TEGRA_UARTA_BASE,
+               .irq            = INT_UARTA,
+               .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
+               .type           = PORT_TEGRA,
+               .iotype         = UPIO_MEM,
+               .regshift       = 2,
+               .uartclk        = 13000000,
+       }, {
+               .flags          = 0,
+       }
+};
+
+static struct platform_device debug_uart = {
+       .name = "serial8250",
+       .id = PLAT8250_DEV_PLATFORM,
+       .dev = {
+               .platform_data = debug_uart_platform_data,
+       },
+};
+
+/* !!!TODO: Change for cardhu (Taken from Ventana) */
+static struct tegra_utmip_config utmi_phy_config[] = {
+       [0] = {
+                       .hssync_start_delay = 0,
+                       .idle_wait_delay = 17,
+                       .elastic_limit = 16,
+                       .term_range_adj = 6,
+                       .xcvr_setup = 15,
+                       .xcvr_lsfslew = 2,
+                       .xcvr_lsrslew = 2,
+       },
+       [1] = {
+                       .hssync_start_delay = 0,
+                       .idle_wait_delay = 17,
+                       .elastic_limit = 16,
+                       .term_range_adj = 6,
+                       .xcvr_setup = 8,
+                       .xcvr_lsfslew = 2,
+                       .xcvr_lsrslew = 2,
+       },
+};
+
+/* !!!TODO: Change for cardhu (Taken from Ventana) */
+static struct tegra_ulpi_config ulpi_phy_config = {
+       /* !!!TODO!!! CABLE DETECT? if so GPIO_PC7 on cardhu */
+       .reset_gpio = TEGRA_GPIO_PG2,
+       .clk = "clk_dev2",
+};
+
+#ifdef CONFIG_BCM4329_RFKILL
+static struct resource cardhu_bcm4329_rfkill_resources[] = {
+       {
+               .name   = "bcm4329_nreset_gpio",
+               .start  = TEGRA_GPIO_PU0,
+               .end    = TEGRA_GPIO_PU0,
+               .flags  = IORESOURCE_IO,
+       },
+       {
+               .name   = "bcm4329_nshutdown_gpio",
+               .start  = TEGRA_GPIO_PK2,
+               .end    = TEGRA_GPIO_PK2,
+               .flags  = IORESOURCE_IO,
+       },
+};
+
+static struct platform_device cardhu_bcm4329_rfkill_device = {
+       .name = "bcm4329_rfkill",
+       .id             = -1,
+       .num_resources  = ARRAY_SIZE(cardhu_bcm4329_rfkill_resources),
+       .resource       = cardhu_bcm4329_rfkill_resources,
+};
+
+static noinline void __init cardhu_bt_rfkill(void)
+{
+       /*Add Clock Resource*/
+       clk_add_alias("bcm4329_32k_clk", cardhu_bcm4329_rfkill_device.name, \
+                               "blink", NULL);
+
+       platform_device_register(&cardhu_bcm4329_rfkill_device);
+
+       return;
+}
+#else
+static inline void cardhu_bt_rfkill(void) { }
+#endif
+
+static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
+       /* name         parent          rate            enabled */
+       { "uarta",      "clk_m",        13000000,       true},
+       { "uartb",      "clk_m",        13000000,       true},
+       { "uartc",      "clk_m",        13000000,       true},
+       { "uartd",      "clk_m",        13000000,       true},
+       { "uarte",      "clk_m",        13000000,       true},
+       { "pll_m",      NULL,           600000000,      true},
+       { "blink",      "clk_32k",      32768,          false},
+       { "pll_p_out4", "pll_p",        24000000,       true },
+       { "pwm",        "clk_32k",      32768,          false},
+       { "blink",      "clk_32k",      32768,          false},
+       { "pll_a",      NULL,           11289600,       true},
+       { "pll_a_out0", NULL,           11289600,       true},
+       { "i2s1",       "pll_a_out0",   11289600,       true},
+       { "i2s2",       "pll_a_out0",   11289600,       true},
+       { "audio",      "pll_a_out0",   11289600,       true},
+       { "audio_2x",   "audio",        22579200,       true},
+       { NULL,         NULL,           0,              0},
+};
+
+static struct tegra_ulpi_config cardhu_ehci2_ulpi_phy_config = {
+       .reset_gpio = TEGRA_GPIO_PV1,
+       .clk = "clk_dev2",
+};
+
+static struct tegra_ehci_platform_data cardhu_ehci2_ulpi_platform_data = {
+       .operating_mode = TEGRA_USB_HOST,
+       .power_down_on_bus_suspend = 0,
+       .phy_config = &cardhu_ehci2_ulpi_phy_config,
+};
+
+static struct tegra_i2c_platform_data cardhu_i2c1_platform_data = {
+       .adapter_nr     = 0,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 400000, 0 },
+};
+
+static struct tegra_i2c_platform_data cardhu_i2c2_platform_data = {
+       .adapter_nr     = 1,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 400000, 0 },
+};
+
+static struct tegra_i2c_platform_data cardhu_i2c3_platform_data = {
+       .adapter_nr     = 2,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 400000, 0 },
+};
+
+static struct tegra_i2c_platform_data cardhu_i2c4_platform_data = {
+       .adapter_nr     = 3,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 400000, 0 },
+       .is_dvc         = true,
+};
+
+static struct tegra_i2c_platform_data cardhu_i2c5_platform_data = {
+       .adapter_nr     = 4,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 400000, 0 },
+};
+
+
+static void cardhu_i2c_init(void)
+{
+       tegra_i2c_device1.dev.platform_data = &cardhu_i2c1_platform_data;
+       tegra_i2c_device2.dev.platform_data = &cardhu_i2c2_platform_data;
+       tegra_i2c_device3.dev.platform_data = &cardhu_i2c3_platform_data;
+       tegra_i2c_device4.dev.platform_data = &cardhu_i2c4_platform_data;
+       tegra_i2c_device5.dev.platform_data = &cardhu_i2c5_platform_data;
+
+       platform_device_register(&tegra_i2c_device5);
+       platform_device_register(&tegra_i2c_device4);
+       platform_device_register(&tegra_i2c_device3);
+       platform_device_register(&tegra_i2c_device2);
+       platform_device_register(&tegra_i2c_device1);
+}
+
+#define GPIO_KEY(_id, _gpio, _iswake)          \
+       {                                       \
+               .code = _id,                    \
+               .gpio = TEGRA_GPIO_##_gpio,     \
+               .active_low = 1,                \
+               .desc = #_id,                   \
+               .type = EV_KEY,                 \
+               .wakeup = _iswake,              \
+               .debounce_interval = 10,        \
+       }
+
+/* !!!TODO!!! Change for cardhu */
+static struct gpio_keys_button cardhu_keys[] = {
+       [0] = GPIO_KEY(KEY_MENU, PQ0, 0),
+       [1] = GPIO_KEY(KEY_HOME, PQ1, 0),
+       [2] = GPIO_KEY(KEY_BACK, PQ2, 0),
+       [3] = GPIO_KEY(KEY_VOLUMEUP, PQ3, 0),
+       [4] = GPIO_KEY(KEY_VOLUMEDOWN, PQ4, 0),
+       [5] = GPIO_KEY(KEY_POWER, PV2, 1),
+};
+
+static struct gpio_keys_platform_data cardhu_keys_platform_data = {
+       .buttons        = cardhu_keys,
+       .nbuttons       = ARRAY_SIZE(cardhu_keys),
+};
+
+static struct platform_device cardhu_keys_device = {
+       .name   = "gpio-keys",
+       .id     = 0,
+       .dev    = {
+               .platform_data  = &cardhu_keys_platform_data,
+       },
+};
+
+static struct resource tegra_rtc_resources[] = {
+       [0] = {
+               .start = TEGRA_RTC_BASE,
+               .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start = INT_RTC,
+               .end = INT_RTC,
+               .flags = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device tegra_rtc_device = {
+       .name = "tegra_rtc",
+       .id   = -1,
+       .resource = tegra_rtc_resources,
+       .num_resources = ARRAY_SIZE(tegra_rtc_resources),
+};
+
+static struct platform_device *cardhu_devices[] __initdata = {
+       &tegra_otg_device,
+       &debug_uart,
+       &tegra_uartb_device,
+       &tegra_uartc_device,
+       &tegra_uartd_device,
+       &tegra_uarte_device,
+       &pmu_device,
+       &tegra_rtc_device,
+       &tegra_udc_device,
+       &tegra_ehci2_device,
+#if defined(CONFIG_TEGRA_IOVMM_SMMU)
+       &tegra_smmu_device,
+#endif
+       &cardhu_keys_device,
+       &tegra_wdt_device,
+       &tegra_avp_device,
+};
+
+static int __init cardhu_touch_init(void)
+{
+       return 0;
+}
+
+
+static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
+       [0] = {
+                       .phy_config = &utmi_phy_config[0],
+                       .operating_mode = TEGRA_USB_HOST,
+                       .power_down_on_bus_suspend = 0,
+       },
+       [1] = {
+                       .phy_config = &ulpi_phy_config,
+                       .operating_mode = TEGRA_USB_HOST,
+                       .power_down_on_bus_suspend = 1,
+       },
+       [2] = {
+                       .phy_config = &utmi_phy_config[1],
+                       .operating_mode = TEGRA_USB_HOST,
+                       .power_down_on_bus_suspend = 0,
+       },
+};
+
+static void cardhu_usb_init(void)
+{
+       tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2];
+       platform_device_register(&tegra_ehci3_device);
+}
+
+struct platform_device *tegra_usb_otg_host_register(void)
+{
+       struct platform_device *pdev;
+       void *platform_data;
+       int val;
+
+       pdev = platform_device_alloc(tegra_ehci1_device.name,
+               tegra_ehci1_device.id);
+       if (!pdev)
+               return NULL;
+
+       val = platform_device_add_resources(pdev, tegra_ehci1_device.resource,
+               tegra_ehci1_device.num_resources);
+       if (val)
+               goto error;
+
+       pdev->dev.dma_mask =  tegra_ehci1_device.dev.dma_mask;
+       pdev->dev.coherent_dma_mask = tegra_ehci1_device.dev.coherent_dma_mask;
+
+       platform_data = kmalloc(sizeof(struct tegra_ehci_platform_data),
+               GFP_KERNEL);
+       if (!platform_data)
+               goto error;
+
+       memcpy(platform_data, &tegra_ehci_pdata[0],
+                               sizeof(struct tegra_ehci_platform_data));
+       pdev->dev.platform_data = platform_data;
+
+       val = platform_device_add(pdev);
+       if (val)
+               goto error_add;
+
+       return pdev;
+
+error_add:
+       kfree(platform_data);
+error:
+       pr_err("%s: failed to add the host contoller device\n", __func__);
+       platform_device_put(pdev);
+       return NULL;
+}
+
+void tegra_usb_otg_host_unregister(struct platform_device *pdev)
+{
+       platform_device_unregister(pdev);
+}
+
+static void __init tegra_cardhu_init(void)
+{
+       tegra_common_init();
+       tegra_clk_init_from_table(cardhu_clk_init_table);
+       cardhu_pinmux_init();
+
+       tegra_ehci2_device.dev.platform_data
+               = &cardhu_ehci2_ulpi_platform_data;
+       platform_add_devices(cardhu_devices, ARRAY_SIZE(cardhu_devices));
+
+       cardhu_sdhci_init();
+       cardhu_i2c_init();
+       cardhu_regulator_init();
+       cardhu_touch_init();
+       cardhu_usb_init();
+       cardhu_panel_init();
+       cardhu_sensors_init();
+       cardhu_bt_rfkill();
+}
+
+MACHINE_START(CARDHU, "cardhu")
+       .boot_params    = 0x80000100,
+       .phys_io        = IO_APB_PHYS,
+       .io_pg_offst    = ((IO_APB_VIRT) >> 18) & 0xfffc,
+       .init_irq       = tegra_init_irq,
+       .init_machine   = tegra_cardhu_init,
+       .map_io         = tegra_map_common_io,
+       .timer          = &tegra_timer,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/board-cardhu.h b/arch/arm/mach-tegra/board-cardhu.h
new file mode 100644 (file)
index 0000000..e62a363
--- /dev/null
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-tegra/board-cardhu.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MACH_TEGRA_BOARD_CARDHU_H
+#define _MACH_TEGRA_BOARD_CARDHU_H
+
+int cardhu_charge_init(void);
+int cardhu_regulator_init(void);
+int cardhu_sdhci_init(void);
+int cardhu_pinmux_init(void);
+int cardhu_panel_init(void);
+int cardhu_sensors_init(void);
+
+#endif