asoc:tegra: fix dam cif programming
Dara Ramesh [Thu, 13 Dec 2012 09:48:24 +0000 (14:48 +0530)]
as per dam spec file chout is fixed to 32bits
so accept chout and ch1 input as 32bit always.

Reviewed-on: http://git-master/r/170931
(cherry picked from commit dd07f40144f763be77ce4e2aea5e7d4d22e6a134)

Change-Id: Ie423bb62e88ca2800b8a9180381685b5e085379f
Signed-off-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-on: http://git-master/r/188287
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

sound/soc/tegra/tegra30_dam.c
sound/soc/tegra/tegra_aic326x.c
sound/soc/tegra/tegra_cs42l73.c
sound/soc/tegra/tegra_max98088.c

index bb42edc..26b65df 100644 (file)
@@ -676,9 +676,13 @@ int tegra30_dam_set_acif(int ifc, int chid, unsigned int audio_channels,
                return -EINVAL;
 
 #ifndef CONFIG_ARCH_TEGRA_3x_SOC
-       /*ch0 takes input as mono/32bit always*/
+       /*ch0 takes input as mono always*/
        if ((chid == dam_ch_in0) &&
-               ((client_channels != 1) || (client_bits != 32)))
+               ((client_channels != 1)))
+               return -EINVAL;
+       /*as per dam spec file chout is fixed to 32 bits*/
+       /*so accept ch0, ch1 and chout as 32bit always*/
+       if (client_bits != 32)
                return -EINVAL;
 #else
        /*ch0 takes input as mono/16bit always*/
index 9b7d0e6..6b63599 100644 (file)
@@ -243,14 +243,17 @@ static int tegra_aic326x_set_dam_cif(int dam_ifc, int srate,
                                srate);
        tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHIN1,
                                srate);
+#ifndef CONFIG_ARCH_TEGRA_3x_SOC
        tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN1,
                channels, bit_size, channels,
-                               bit_size);
-#ifndef CONFIG_ARCH_TEGRA_3x_SOC
+                               32);
        tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT,
                channels, bit_size, channels,
                                32);
 #else
+       tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN1,
+               channels, bit_size, channels,
+                               bit_size);
        tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT,
                channels, bit_size, channels,
                                bit_size);
index efd7174..b1d9cfe 100644 (file)
@@ -186,14 +186,17 @@ static int tegra_cs42l73_set_dam_cif(int dam_ifc, int srate,
                                srate);
        tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHIN1,
                                srate);
+#ifndef CONFIG_ARCH_TEGRA_3x_SOC
        tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN1,
                channels, bit_size, channels,
-                               bit_size);
-#ifndef CONFIG_ARCH_TEGRA_3x_SOC
+                               32);
        tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT,
                channels, bit_size, channels,
                                32);
 #else
+       tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN1,
+               channels, bit_size, channels,
+                               bit_size);
        tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT,
                channels, bit_size, channels,
                                bit_size);
index 8190758..714943a 100644 (file)
@@ -181,14 +181,17 @@ static int tegra_max98088_set_dam_cif(int dam_ifc, int srate,
                                srate);
        tegra30_dam_set_samplerate(dam_ifc, TEGRA30_DAM_CHIN1,
                                srate);
+#ifndef CONFIG_ARCH_TEGRA_3x_SOC
        tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN1,
                channels, bit_size, channels,
-                               bit_size);
-#ifndef CONFIG_ARCH_TEGRA_3x_SOC
+                               32);
        tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT,
                channels, bit_size, channels,
                                32);
 #else
+       tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHIN1,
+               channels, bit_size, channels,
+                               bit_size);
        tegra30_dam_set_acif(dam_ifc, TEGRA30_DAM_CHOUT,
                channels, bit_size, channels,
                                bit_size);