ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API
Lorenzo Pieralisi [Fri, 7 Sep 2012 05:39:15 +0000 (10:39 +0530)]
When a CPU is hotplugged out caches that reside in its power domain
lose their contents and so must be cleaned to the next memory level.

Currently, __cpu_disable calls flush_cache_all() that for new generation
processor like A15/A7 ends up cleaning and invalidating all cache levels
up to Level of Coherency, which includes the unified L2.

This ends up being a waste of cycles since the L2 cache contents are not
lost on power down.

This patch updates __cpu_disable to use the new LoUIS API cache operations.

Acked-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Change-Id: Ib95a626f00ff0ab8c1b974e57f62ebef92175510
Reviewed-on: http://git-master/r/147784
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/kernel/smp.c

index aed35c6..dee11a0 100644 (file)
@@ -241,8 +241,11 @@ int __cpuinit __cpu_disable(void)
        /*
         * Flush user cache and TLB mappings, and then remove this CPU
         * from the vm mask set of all processes.
+        *
+        * Caches are flushed to the Level of Unification Inner Shareable
+        * to write-back dirty lines to unified caches shared by all CPUs.
         */
-       flush_cache_all();
+       flush_cache_louis();
        local_flush_tlb_all();
 
        read_lock(&tasklist_lock);