[IA64] Two trivial spelling fixes
Joe Perches [Wed, 19 Dec 2007 01:02:21 +0000 (17:02 -0800)]
s/addres/address/
s/performanc/performance/

Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>

arch/ia64/sn/pci/tioce_provider.c
include/asm-ia64/hw_irq.h

index cee9379..e1a3e19 100644 (file)
@@ -41,7 +41,7 @@
  *     } else
  *             do desired mmr access
  *
- * According to hw, we can use reads instead of writes to the above addres
+ * According to hw, we can use reads instead of writes to the above address
  *
  * Note this WAR can only to be used for accessing internal MMR's in the
  * TIOCE Coretalk Address Range 0x0 - 0x07ff_ffff.  This includes the
index bba5baa..7e6e377 100644 (file)
@@ -63,7 +63,7 @@ extern int ia64_last_device_vector;
 #define IA64_NUM_DEVICE_VECTORS                (IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1)
 
 #define IA64_MCA_RENDEZ_VECTOR         0xe8    /* MCA rendez interrupt */
-#define IA64_PERFMON_VECTOR            0xee    /* performanc monitor interrupt vector */
+#define IA64_PERFMON_VECTOR            0xee    /* performance monitor interrupt vector */
 #define IA64_TIMER_VECTOR              0xef    /* use highest-prio group 15 interrupt for timer */
 #define        IA64_MCA_WAKEUP_VECTOR          0xf0    /* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */
 #define IA64_IPI_LOCAL_TLB_FLUSH       0xfc    /* SMP flush local TLB */