ASoC: Fix WM8996 24.576MHz clock operation
Mark Brown [Sat, 10 Dec 2011 12:38:32 +0000 (20:38 +0800)]
commit 37d5993c5cc9bc83762ae1b5bd287438022e8afe upstream.

Record the clock after the divider as that is what all SYSCLK users see.
Without this the other clock configuration in the device comes out at
half rate.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

Change-Id: Ifd4d1165bc59b4cb35a3d30e43ebba442c67a68c
Reviewed-on: http://git-master/r/74167
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>

sound/soc/codecs/wm8996.c

index c9c4e5c..5c40874 100644 (file)
@@ -1895,6 +1895,7 @@ static int wm8996_set_sysclk(struct snd_soc_dai *dai,
                break;
        case 24576000:
                ratediv = WM8996_SYSCLK_DIV;
+               wm8996->sysclk /= 2;
        case 12288000:
                snd_soc_update_bits(codec, WM8996_AIF_RATE,
                                    WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);