gianfar: Add support etsec2.0 registers.
Sandeep Gopalpet [Mon, 2 Nov 2009 07:03:28 +0000 (07:03 +0000)]
This patch adds support for etsec2.0 regsiters

Signed-off-by: Sandeep Gopalpet <Sandeep.Kumar@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

drivers/net/gianfar.h

index 5ae769d..08518c2 100644 (file)
@@ -566,25 +566,32 @@ struct gfar_stats {
 
 struct gfar {
        u32     tsec_id;        /* 0x.000 - Controller ID register */
-       u8      res1[12];
+       u32     tsec_id2;       /* 0x.004 - Controller ID2 register */
+       u8      res1[8];
        u32     ievent;         /* 0x.010 - Interrupt Event Register */
        u32     imask;          /* 0x.014 - Interrupt Mask Register */
        u32     edis;           /* 0x.018 - Error Disabled Register */
-       u8      res2[4];
+       u32     emapg;          /* 0x.01c - Group Error mapping register */
        u32     ecntrl;         /* 0x.020 - Ethernet Control Register */
        u32     minflr;         /* 0x.024 - Minimum Frame Length Register */
        u32     ptv;            /* 0x.028 - Pause Time Value Register */
        u32     dmactrl;        /* 0x.02c - DMA Control Register */
        u32     tbipa;          /* 0x.030 - TBI PHY Address Register */
-       u8      res3[88];
+       u8      res2[28];
+       u32     fifo_rx_pause;  /* 0x.050 - FIFO receive pause start threshold
+                                       register */
+       u32     fifo_rx_pause_shutoff;  /* x.054 - FIFO receive starve shutoff
+                                               register */
+       u32     fifo_rx_alarm;  /* 0x.058 - FIFO receive alarm start threshold
+                                               register */
+       u32     fifo_rx_alarm_shutoff;  /*0x.05c - FIFO receive alarm  starve
+                                               shutoff register */
+       u8      res3[44];
        u32     fifo_tx_thr;    /* 0x.08c - FIFO transmit threshold register */
        u8      res4[8];
        u32     fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
        u32     fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
-       u8      res5[4];
-       u32     fifo_rx_pause;  /* 0x.0a4 - FIFO receive pause threshold register */
-       u32     fifo_rx_alarm;  /* 0x.0a8 - FIFO receive alarm threshold register */
-       u8      res6[84];
+       u8      res5[96];
        u32     tctrl;          /* 0x.100 - Transmit Control Register */
        u32     tstat;          /* 0x.104 - Transmit Status Register */
        u32     dfvlan;         /* 0x.108 - Default VLAN Control word */
@@ -635,7 +642,11 @@ struct gfar {
        u8      res12[8];
        u32     rxic;           /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
        u32     rqueue;         /* 0x.314 - Receive queue control register */
-       u8      res13[24];
+       u32     rir0;           /* 0x.318 - Ring mapping register 0 */
+       u32     rir1;           /* 0x.31c - Ring mapping register 1 */
+       u32     rir2;           /* 0x.320 - Ring mapping register 2 */
+       u32     rir3;           /* 0x.324 - Ring mapping register 3 */
+       u8      res13[8];
        u32     rbifx;          /* 0x.330 - Receive bit field extract control register */
        u32     rqfar;          /* 0x.334 - Receive queue filing table address register */
        u32     rqfcr;          /* 0x.338 - Receive queue filing table control register */
@@ -684,7 +695,7 @@ struct gfar {
        u32     maxfrm;         /* 0x.510 - Maximum Frame Length Register */
        u8      res18[12];
        u8      gfar_mii_regs[24];      /* See gianfar_phy.h */
-       u8      res19[4];
+       u32     ifctrl;         /* 0x.538 - Interface control register */
        u32     ifstat;         /* 0x.53c - Interface Status Register */
        u32     macstnaddr1;    /* 0x.540 - Station Address Part 1 Register */
        u32     macstnaddr2;    /* 0x.544 - Station Address Part 2 Register */
@@ -745,8 +756,30 @@ struct gfar {
        u8      res23c[248];
        u32     attr;           /* 0x.bf8 - Attributes Register */
        u32     attreli;        /* 0x.bfc - Attributes Extract Length and Extract Index Register */
-       u8      res24[1024];
-
+       u8      res24[688];
+       u32     isrg0;          /* 0x.eb0 - Interrupt steering group 0 register */
+       u32     isrg1;          /* 0x.eb4 - Interrupt steering group 1 register */
+       u32     isrg2;          /* 0x.eb8 - Interrupt steering group 2 register */
+       u32     isrg3;          /* 0x.ebc - Interrupt steering group 3 register */
+       u8      res25[16];
+       u32     rxic0;          /* 0x.ed0 - Ring 0 Rx interrupt coalescing */
+       u32     rxic1;          /* 0x.ed4 - Ring 1 Rx interrupt coalescing */
+       u32     rxic2;          /* 0x.ed8 - Ring 2 Rx interrupt coalescing */
+       u32     rxic3;          /* 0x.edc - Ring 3 Rx interrupt coalescing */
+       u32     rxic4;          /* 0x.ee0 - Ring 4 Rx interrupt coalescing */
+       u32     rxic5;          /* 0x.ee4 - Ring 5 Rx interrupt coalescing */
+       u32     rxic6;          /* 0x.ee8 - Ring 6 Rx interrupt coalescing */
+       u32     rxic7;          /* 0x.eec - Ring 7 Rx interrupt coalescing */
+       u8      res26[32];
+       u32     txic0;          /* 0x.f10 - Ring 0 Tx interrupt coalescing */
+       u32     txic1;          /* 0x.f14 - Ring 1 Tx interrupt coalescing */
+       u32     txic2;          /* 0x.f18 - Ring 2 Tx interrupt coalescing */
+       u32     txic3;          /* 0x.f1c - Ring 3 Tx interrupt coalescing */
+       u32     txic4;          /* 0x.f20 - Ring 4 Tx interrupt coalescing */
+       u32     txic5;          /* 0x.f24 - Ring 5 Tx interrupt coalescing */
+       u32     txic6;          /* 0x.f28 - Ring 6 Tx interrupt coalescing */
+       u32     txic7;          /* 0x.f2c - Ring 7 Tx interrupt coalescing */
+       u8      res27[208];
 };
 
 /* Flags related to gianfar device features */