video: tegra: dsi: Refactor code in tegra_dsi_hw_init()
Kevin Huang [Fri, 4 Nov 2011 18:40:21 +0000 (11:40 -0700)]
Reviewed-on: http://git-master/r/54824
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Tested-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
(cherry picked from commit 4681815651f5949840815a03698d55ec8186796c)

Change-Id: I5553b52806c63f8fb1fdc38f151a144ec103bcc5
Reviewed-on: http://git-master/r/61617
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Tested-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rf733836f46f9afb42b5d680683d98e04c4a0e776

drivers/video/tegra/dc/dsi.c

index 2a9e127..877c460 100644 (file)
@@ -1082,38 +1082,15 @@ static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi)
        tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
 }
 
-static int tegra_dsi_init_hw(struct tegra_dc *dc,
-                               struct tegra_dc_dsi_data *dsi)
+static void tegra_dsi_pad_caliberation(struct tegra_dc_dsi_data *dsi)
 {
        u32 val;
-       u32 i;
-
-       val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
-       tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
-
-       tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
-       if (dsi->info.dsi_instance) {
-               /* TODO:Set the misc register */
-       }
-
-       /* TODO: only need to change the timing for bta */
-       tegra_dsi_set_phy_timing(dsi);
 
-       if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
-               tegra_dsi_stop_dc_stream(dc, dsi);
-
-       /* Initializing DSI registers */
-       for (i = 0; i < ARRAY_SIZE(init_reg); i++)
-               tegra_dsi_writel(dsi, 0, init_reg[i]);
-
-       tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
-       /* Initialize DSI_PAD_CONTROL register. */
        val =   DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
                DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
                DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
                DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
                DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
-
        if (!dsi->ulpm) {
                val |=  DSI_PAD_CONTROL_PAD_PDIO(0) |
                        DSI_PAD_CONTROL_PAD_PDIO_CLK(0) |
@@ -1136,6 +1113,35 @@ static int tegra_dsi_init_hw(struct tegra_dc *dc,
 
        val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
        tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
+}
+
+static int tegra_dsi_init_hw(struct tegra_dc *dc,
+                                               struct tegra_dc_dsi_data *dsi)
+{
+       u32 val;
+       u32 i;
+
+       val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
+       tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
+
+       tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
+       if (dsi->info.dsi_instance) {
+               /* TODO:Set the misc register*/
+       }
+
+       /* TODO: only need to change the timing for bta */
+       tegra_dsi_set_phy_timing(dsi);
+
+       if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
+               tegra_dsi_stop_dc_stream(dc, dsi);
+
+       /* Initializing DSI registers */
+       for (i = 0; i < ARRAY_SIZE(init_reg); i++)
+               tegra_dsi_writel(dsi, 0, init_reg[i]);
+
+       tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
+
+       tegra_dsi_pad_caliberation(dsi);
 
        val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE);
        tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);