usb: xhci: tegra: set ss_clk at 120MHz before fw loading
Ajay Gupta [Mon, 4 Mar 2013 20:26:16 +0000 (12:26 -0800)]
This is needed to avoid SS device getting in compliance.

Bug 1246619

Change-Id: I3cbb95f318aae70573d392729f5b8bf069b484db
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/206462
Reviewed-by: Henry Lin <henryl@nvidia.com>
Reviewed-by: Jui Chang Kuo <jckuo@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
(cherry picked from commit 892f2022442f45b58109de3f304829e7a2c43907)
Reviewed-on: http://git-master/r/208863
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit

drivers/usb/host/xhci-tegra.c

index 08ef726..395b23b 100644 (file)
@@ -1661,6 +1661,15 @@ tegra_xhci_host_partition_elpg_exit(struct tegra_xhci_hcd *tegra)
 
        tegra_xhci_ss_partition_elpg_exit(tegra);
 
+       /* Change SS clock source to HSIC_480 and set ss_clk at 120MHz */
+       if (clk_get_rate(tegra->ss_clk) == 12000000) {
+               clk_set_rate(tegra->ss_clk,  3000 * 1000);
+               clk_set_parent(tegra->ss_clk, tegra->pll_u_480M);
+
+               /* clear ovrd bits when SS freq is being increased */
+               tegra_xhci_rx_idle_mode_override(tegra, false);
+       }
+
        /* Load firmware */
        xhci_dbg(xhci, "%s: elpg_exit: loading firmware from pmc.\n"
                        "ss (p1=0x%x, p2=0x%x, p3=0x%x), "