ARM: tegra: clock: Fix emulation clock table
Alex Frid [Sun, 1 Apr 2012 07:28:46 +0000 (00:28 -0700)]
Configure PLLC on emulation platforms after SCLK is switched to PLLP.
This would avoid failure in case when emulation initialization script
set PLLC as SCLK source.

Change-Id: Ie0f48c066f6df7f6f3c67858de7e9d7608dcb7ff
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/93730
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/mach-tegra/common.c

index 0127146..46ddf91 100644 (file)
@@ -194,12 +194,12 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
        { "pll_p_out2", "pll_p",        48000000,       false },
        { "pll_p_out3", "pll_p",        72000000,       true },
        { "pll_m_out1", "pll_m",        275000000,      true },
-       { "pll_c",      NULL,           ULONG_MAX,      false },
-       { "pll_c_out1", "pll_c",        208000000,      false },
        { "pll_p_out4", "pll_p",        108000000,      false },
        { "sclk",       "pll_p_out4",   108000000,      true },
        { "hclk",       "sclk",         108000000,      true },
        { "pclk",       "hclk",         54000000,       true },
+       { "pll_c",      NULL,           ULONG_MAX,      false },
+       { "pll_c_out1", "pll_c",        208000000,      false },
 #endif
 #ifdef CONFIG_TEGRA_SLOW_CSITE
        { "csite",      "clk_m",        1000000,        true },