video: tegra: dc: use at least 500MHz pll for HDMI
Jon Mayo [Tue, 8 Jan 2013 19:20:55 +0000 (11:20 -0800)]
Bug 1167856
Bug 1185882

Change-Id: I3acd4b36745a00eb77e9c70cc6f3e8317ccb060a
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/189628
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

drivers/video/tegra/dc/hdmi.c

index 0b29830..1b00552 100644 (file)
@@ -1906,7 +1906,10 @@ static long tegra_dc_hdmi_setup_clk(struct tegra_dc *dc, struct clk *clk)
         * as out0 is 1/2 of the actual PLL output.
         */
 
-       rate = dc->mode.pclk * 4;
+       rate = dc->mode.pclk * 2;
+       while (rate < 500000000)
+               rate *= 2;
+
        if (rate != clk_get_rate(base_clk))
                clk_set_rate(base_clk, rate);