[ARM] 3021/1: Interrupt 0 bug fix for ixp4xx
Kenneth Tan [Tue, 18 Oct 2005 06:53:35 +0000 (07:53 +0100)]
Patch from Kenneth Tan

The get_irqnr_and_base subroutine of ixp4xx does not take interrupt 0 condition into account properly. We should not perform "subs" here. The Z flag will be set when interrupt 0 occur, which resulting "movne r1, sp" in the caller routine (irq_handler) not being executed.

When interrupt 0 occur:
o if CONFIG_CPU_IXP46X is not set, "subs" will set the Z flag and return
o if CONFIG_CPU_IXP46X is set, codes in upper interrupt handling will be trigerred. But since this is not supper interrupt, the "cmp" in the upper interrupt handling portion will set the Z flag and return

Signed-off-by: Kenneth Tan <chong.yin.tan@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

include/asm-arm/arch-ixp4xx/entry-macro.S

index 455da64..323b0bc 100644 (file)
                ldr     \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
                ldr     \irqstat, [\irqstat]            @ get interrupts
                cmp     \irqstat, #0
-               beq     1001f
+               beq     1001f                           @ upper IRQ?
                clz     \irqnr, \irqstat
                mov     \base, #31
-               subs    \irqnr, \base, \irqnr
+               sub     \irqnr, \base, \irqnr
+               b       1002f                           @ lower IRQ being
+                                                       @ handled
 
 1001:
                /*
                 * IXP465 has an upper IRQ status register
                 */
 #if defined(CONFIG_CPU_IXP46X)
-               bne     1002f
                ldr     \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
                ldr     \irqstat, [\irqstat]            @ get upper interrupts
                mov     \irqnr, #63
                clz     \irqstat, \irqstat
                cmp     \irqstat, #32
                subne   \irqnr, \irqnr, \irqstat
-1002:
 #endif
+1002:
                .endm