ARM: Tegra: Cardhu: Adding SDMMC drive strengths
Pavan Kunapuli [Fri, 22 Jul 2011 13:25:38 +0000 (18:25 +0530)]
Configuring the drive strengths for SDMMC1, SDMMC3
and SDMMC4.

Bug 799568
Bug 826694

Original-Change-Id: Ib18c002993eddaf622f48faa0b4e4c9deb0f8e3c
Reviewed-on: http://git-master/r/42608
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: Raf1d57275c48839cdb4913c3b028b4c2ad176952

arch/arm/mach-tegra/board-cardhu-pinmux.c

index 23cfe36..6781caf 100644 (file)
@@ -85,6 +85,19 @@ static __initdata struct tegra_drive_pingroup_config cardhu_drive_pinmux[] = {
 
        /* UART3 */
        SET_DRIVE(UART3,        DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+       /* SDMMC1 */
+       SET_DRIVE(SDIO1,        DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+       /* SDMMC3 */
+       SET_DRIVE(SDIO3,        DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+       /* SDMMC4 */
+       SET_DRIVE(GMA,          DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+       SET_DRIVE(GMB,          DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+       SET_DRIVE(GMC,          DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+       SET_DRIVE(GMD,          DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
 };
 
 #define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io)      \