ARM: tegra: dvfs: Enable DFLL/PLL auto-switch by default
Alex Frid [Sat, 18 May 2013 00:55:38 +0000 (17:55 -0700)]
Bug 1291764

Change-Id: Idab2e02b60fee56a2af2b11c9121af2ca6b15dda
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/230032
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Tested-by: Yu-Huan Hsu <yhsu@nvidia.com>

arch/arm/mach-tegra/Kconfig

index 1c45437..fa308f9 100644 (file)
@@ -842,7 +842,7 @@ config TEGRA_USE_DFLL_RANGE
        int "Default CPU DFLL operating range"
        depends on ARCH_TEGRA_HAS_CL_DVFS
        range 0 2
-       default "1" if TEGRA_SILICON_PLATFORM
+       default "2" if TEGRA_SILICON_PLATFORM
        default "0"
        help
          Defines default range for dynamic frequency lock loop (DFLL)