ARM: tegra: pluto: memory: Updated the 2GB table
Jay Bhukhanwala [Wed, 24 Jul 2013 23:44:27 +0000 (16:44 -0700)]
The revision for the table is now 0x42

Bug 1288185

Change-Id: I1fcdb882fd68cf500685c5583619cbae02671c47
Signed-off-by: Jay Bhukhanwala <jbhukhanwala@nvidia.com>
Reviewed-on: http://git-master/r/237401
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arch/arm/mach-tegra/board-pluto-memory.c

index f5ecd7b..0f1f00b 100644 (file)
 #include "fuse.h"
 #include "devices.h"
 
-static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
+static struct tegra11_emc_table e1580_fa164a1ma_gd_f_table[] = {
        {
-               0x41,       /* Rev 4.0.3 */
+               0x42,       /* Rev 4.0.3 */
                12750,      /* SDRAM frequency */
                900,        /* min voltage */
                "pll_p",    /* clock source id */
-               0x4000003e, /* CLK_SOURCE_EMC */
-               99,         /* number of burst_regs */
+               0x4400003e, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
                30,         /* number of trim_regs (each channel) */
                11,         /* number of up_down_regs */
                {
@@ -88,10 +88,10 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0001aa86, /* EMC_FBIO_CFG5 */
                        0x005800a8, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00048000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS7 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE4 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE6 */
@@ -111,16 +111,16 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0000003f, /* EMC_DSR_VTTGEN_DRV */
                        0x00000000, /* EMC_TXDSRVTTGEN */
                        0x02000100, /* EMC_FBIO_SPARE */
-                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000301, /* EMC_CTT_TERM_CTRL */
                        0x00064000, /* EMC_ZCAL_INTERVAL */
-                       0x0000000f, /* EMC_ZCAL_WAIT_CNT */
-                       0x000f000f, /* EMC_MRS_WAIT_CNT */
-                       0x000f000f, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000010, /* EMC_ZCAL_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
                        0x00000000, /* EMC_CTT */
                        0x00000000, /* EMC_CTT_DURATION */
-                       0x80000165, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x80000164, /* EMC_DYN_SELF_REF_CONTROL */
                        0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
                        0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
                        0x40040001, /* MC_EMEM_ARB_CFG */
@@ -141,32 +141,33 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00090402, /* MC_EMEM_ARB_DA_COVERS */
                        0x77c30303, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x0004032c, /* EMC_SEL_DPD_CTRL */
                },
                {
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000004, /* EMC_FBIO_CFG6 */
                        0x00000007, /* EMC_QUSE */
-                       0x00000003, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT */
                        0x00000005, /* EMC_EINPUT_DURATION */
-                       0x00048000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000b, /* EMC_QSAFE */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x0000000d, /* EMC_RDV */
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x20820800, /* EMC_XM2DQSPADCTRL3 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ0 */
-                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR0 */
                        0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS3 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS3 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ3 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -178,27 +179,27 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000004, /* EMC_FBIO_CFG6 */
                        0x00000007, /* EMC_QUSE */
-                       0x00000003, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT */
                        0x00000005, /* EMC_EINPUT_DURATION */
-                       0x00048000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000b, /* EMC_QSAFE */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x0000000d, /* EMC_RDV */
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x20820800, /* EMC_XM2DQSPADCTRL3 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ0 */
-                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR0 */
                        0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS3 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS3 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ3 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -207,7 +208,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000000, /* EMC_DLL_XFORM_QUSE3 */
                },
                {
-                       0x0000000e, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00000007, /* MC_PTSA_GRANT_DECREMENT */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
@@ -218,8 +219,12 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+                       0x4E564441, /* System Verification tag */
+                       0x04010502, /* Reg_tool Version */
+                       0x02000100, /* DVFS_tool Version */
+                       12750,      /* SDRAM Frequency */
                },
-               0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x00000014, /* EMC_ZCAL_WAIT_CNT after clock change */
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
                0xf320000e, /* EMC_CFG */
                0x00000000, /* Mode Register 0 */
@@ -229,12 +234,12 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                57820,      /* expected dvfs latency (ns) */
        },
        {
-               0x41,       /* Rev 4.0.3 */
+               0x42,       /* Rev 4.0.3 */
                20400,      /* SDRAM frequency */
                900,        /* min voltage */
                "pll_p",    /* clock source id */
-               0x40000026, /* CLK_SOURCE_EMC */
-               99,         /* number of burst_regs */
+               0x44000026, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
                30,         /* number of trim_regs (each channel) */
                11,         /* number of up_down_regs */
                {
@@ -284,10 +289,10 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0001aa86, /* EMC_FBIO_CFG5 */
                        0x005800a8, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00048000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS7 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE4 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE6 */
@@ -307,11 +312,11 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0000003f, /* EMC_DSR_VTTGEN_DRV */
                        0x00000000, /* EMC_TXDSRVTTGEN */
                        0x02000100, /* EMC_FBIO_SPARE */
-                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000301, /* EMC_CTT_TERM_CTRL */
                        0x00064000, /* EMC_ZCAL_INTERVAL */
-                       0x0000000f, /* EMC_ZCAL_WAIT_CNT */
-                       0x000f000f, /* EMC_MRS_WAIT_CNT */
-                       0x000f000f, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000010, /* EMC_ZCAL_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
                        0x00000000, /* EMC_CTT */
@@ -337,32 +342,33 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00090402, /* MC_EMEM_ARB_DA_COVERS */
                        0x74e30303, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x0004032c, /* EMC_SEL_DPD_CTRL */
                },
                {
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000004, /* EMC_FBIO_CFG6 */
                        0x00000007, /* EMC_QUSE */
-                       0x00000003, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT */
                        0x00000005, /* EMC_EINPUT_DURATION */
-                       0x00048000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000b, /* EMC_QSAFE */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x0000000d, /* EMC_RDV */
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x20820800, /* EMC_XM2DQSPADCTRL3 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ0 */
-                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR0 */
                        0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS3 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS3 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ3 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -374,27 +380,27 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000004, /* EMC_FBIO_CFG6 */
                        0x00000007, /* EMC_QUSE */
-                       0x00000003, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT */
                        0x00000005, /* EMC_EINPUT_DURATION */
-                       0x00048000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000b, /* EMC_QSAFE */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x0000000d, /* EMC_RDV */
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x20820800, /* EMC_XM2DQSPADCTRL3 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ0 */
-                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR0 */
                        0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS3 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS3 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ3 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -403,7 +409,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000000, /* EMC_DLL_XFORM_QUSE3 */
                },
                {
-                       0x00000014, /* MC_PTSA_GRANT_DECREMENT */
+                       0x0000000a, /* MC_PTSA_GRANT_DECREMENT */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */
@@ -414,8 +420,12 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+                       0x4E564441, /* System Verification tag */
+                       0x04010600, /* Reg_tool Version */
+                       0x02000100, /* DVFS_tool Version */
+                       20400,      /* SDRAM Frequency */
                },
-               0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x00000014, /* EMC_ZCAL_WAIT_CNT after clock change */
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
                0xf320000e, /* EMC_CFG */
                0x00000000, /* Mode Register 0 */
@@ -425,12 +435,12 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                35610,      /* expected dvfs latency (ns) */
        },
        {
-               0x41,       /* Rev 4.0.3 */
+               0x42,       /* Rev 4.0.3 */
                40800,      /* SDRAM frequency */
                900,        /* min voltage */
                "pll_p",    /* clock source id */
-               0x40000012, /* CLK_SOURCE_EMC */
-               99,         /* number of burst_regs */
+               0x44000012, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
                30,         /* number of trim_regs (each channel) */
                11,         /* number of up_down_regs */
                {
@@ -480,10 +490,10 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0001aa86, /* EMC_FBIO_CFG5 */
                        0x005800a8, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00048000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS7 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE4 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE6 */
@@ -503,11 +513,11 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0000003f, /* EMC_DSR_VTTGEN_DRV */
                        0x00000000, /* EMC_TXDSRVTTGEN */
                        0x02000100, /* EMC_FBIO_SPARE */
-                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000301, /* EMC_CTT_TERM_CTRL */
                        0x00064000, /* EMC_ZCAL_INTERVAL */
-                       0x0000000f, /* EMC_ZCAL_WAIT_CNT */
-                       0x000f000f, /* EMC_MRS_WAIT_CNT */
-                       0x000f000f, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000010, /* EMC_ZCAL_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
                        0x00000000, /* EMC_CTT */
@@ -533,32 +543,33 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00090402, /* MC_EMEM_ARB_DA_COVERS */
                        0x73030303, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x0004032c, /* EMC_SEL_DPD_CTRL */
                },
                {
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000004, /* EMC_FBIO_CFG6 */
                        0x00000007, /* EMC_QUSE */
-                       0x00000003, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT */
                        0x00000005, /* EMC_EINPUT_DURATION */
-                       0x00048000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000b, /* EMC_QSAFE */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x0000000d, /* EMC_RDV */
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x20820800, /* EMC_XM2DQSPADCTRL3 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ0 */
-                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR0 */
                        0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS3 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS3 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ3 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -570,27 +581,27 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000004, /* EMC_FBIO_CFG6 */
                        0x00000007, /* EMC_QUSE */
-                       0x00000003, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT */
                        0x00000005, /* EMC_EINPUT_DURATION */
-                       0x00048000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000b, /* EMC_QSAFE */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x0000000d, /* EMC_RDV */
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x20820800, /* EMC_XM2DQSPADCTRL3 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ0 */
-                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR0 */
                        0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS3 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS3 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ3 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -599,7 +610,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000000, /* EMC_DLL_XFORM_QUSE3 */
                },
                {
-                       0x0000002a, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00000015, /* MC_PTSA_GRANT_DECREMENT */
                        0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */
                        0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */
                        0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */
@@ -610,8 +621,12 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+                       0x4E564441, /* System Verification tag */
+                       0x04010600, /* Reg_tool Version */
+                       0x02000100, /* DVFS_tool Version */
+                       40800,      /* SDRAM Frequency */
                },
-               0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x00000014, /* EMC_ZCAL_WAIT_CNT after clock change */
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
                0xf320000e, /* EMC_CFG */
                0x00000000, /* Mode Register 0 */
@@ -621,12 +636,12 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                20850,      /* expected dvfs latency (ns) */
        },
        {
-               0x41,       /* Rev 4.0.3 */
+               0x42,       /* Rev 4.0.3 */
                68000,      /* SDRAM frequency */
                900,        /* min voltage */
                "pll_p",    /* clock source id */
-               0x4000000a, /* CLK_SOURCE_EMC */
-               99,         /* number of burst_regs */
+               0x4400000a, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
                30,         /* number of trim_regs (each channel) */
                11,         /* number of up_down_regs */
                {
@@ -676,10 +691,10 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0001aa86, /* EMC_FBIO_CFG5 */
                        0x005800a8, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00048000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS7 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE4 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE6 */
@@ -699,11 +714,11 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0000003f, /* EMC_DSR_VTTGEN_DRV */
                        0x00000000, /* EMC_TXDSRVTTGEN */
                        0x02000100, /* EMC_FBIO_SPARE */
-                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000301, /* EMC_CTT_TERM_CTRL */
                        0x00064000, /* EMC_ZCAL_INTERVAL */
                        0x00000019, /* EMC_ZCAL_WAIT_CNT */
-                       0x000f000f, /* EMC_MRS_WAIT_CNT */
-                       0x000f000f, /* EMC_MRS_WAIT_CNT2 */
+                       0x00100010, /* EMC_MRS_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
                        0x00000000, /* EMC_CTT */
@@ -729,32 +744,33 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00090402, /* MC_EMEM_ARB_DA_COVERS */
                        0x72630403, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x0004032c, /* EMC_SEL_DPD_CTRL */
                },
                {
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000004, /* EMC_FBIO_CFG6 */
                        0x00000007, /* EMC_QUSE */
-                       0x00000003, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT */
                        0x00000005, /* EMC_EINPUT_DURATION */
-                       0x00048000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000b, /* EMC_QSAFE */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x0000000d, /* EMC_RDV */
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x20820800, /* EMC_XM2DQSPADCTRL3 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ0 */
-                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR0 */
                        0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS3 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS3 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ3 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -766,27 +782,27 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000004, /* EMC_FBIO_CFG6 */
                        0x00000007, /* EMC_QUSE */
-                       0x00000003, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT */
                        0x00000005, /* EMC_EINPUT_DURATION */
-                       0x00048000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000b, /* EMC_QSAFE */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x0000000d, /* EMC_RDV */
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x20820800, /* EMC_XM2DQSPADCTRL3 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ0 */
-                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR0 */
                        0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS3 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ1 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ2 */
-                       0x0006c000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS3 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000c0000, /* EMC_DLL_XFORM_DQ3 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -795,7 +811,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000000, /* EMC_DLL_XFORM_QUSE3 */
                },
                {
-                       0x00000046, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00000023, /* MC_PTSA_GRANT_DECREMENT */
                        0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */
                        0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */
                        0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */
@@ -806,8 +822,12 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+                       0x4E564441, /* System Verification tag */
+                       0x04010600, /* Reg_tool Version */
+                       0x02000100, /* DVFS_tool Version */
+                       68000,      /* SDRAM Frequency */
                },
-               0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x00000014, /* EMC_ZCAL_WAIT_CNT after clock change */
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
                0xf320000e, /* EMC_CFG */
                0x00000000, /* Mode Register 0 */
@@ -817,12 +837,12 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                10720,      /* expected dvfs latency (ns) */
        },
        {
-               0x41,       /* Rev 4.0.3 */
+               0x42,       /* Rev 4.0.3 */
                102000,     /* SDRAM frequency */
                900,        /* min voltage */
                "pll_p",    /* clock source id */
-               0x40000006, /* CLK_SOURCE_EMC */
-               99,         /* number of burst_regs */
+               0x44000006, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
                30,         /* number of trim_regs (each channel) */
                11,         /* number of up_down_regs */
                {
@@ -872,10 +892,10 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0001aa86, /* EMC_FBIO_CFG5 */
                        0x005800a8, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00048000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00048000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00078000, /* EMC_DLL_XFORM_DQS7 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE4 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE6 */
@@ -891,20 +911,20 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x77ffc004, /* EMC_XM2CLKPADCTRL */
                        0x81f1f008, /* EMC_XM2COMPPADCTRL */
                        0x00000000, /* EMC_XM2VTTGENPADCTRL */
-                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
                        0x0000003f, /* EMC_DSR_VTTGEN_DRV */
                        0x00000000, /* EMC_TXDSRVTTGEN */
                        0x02000100, /* EMC_FBIO_SPARE */
-                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000301, /* EMC_CTT_TERM_CTRL */
                        0x00064000, /* EMC_ZCAL_INTERVAL */
                        0x00000025, /* EMC_ZCAL_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT2 */
+                       0x00100010, /* EMC_MRS_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
                        0x00000000, /* EMC_CTT */
                        0x00000000, /* EMC_CTT_DURATION */
-                       0x8000040c, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
                        0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
                        0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
                        0x08000001, /* MC_EMEM_ARB_CFG */
@@ -925,12 +945,13 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00090403, /* MC_EMEM_ARB_DA_COVERS */
                        0x72430504, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x0004032c, /* EMC_SEL_DPD_CTRL */
                },
                {
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000004, /* EMC_FBIO_CFG6 */
                        0x00000007, /* EMC_QUSE */
-                       0x00000003, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT */
                        0x00000005, /* EMC_EINPUT_DURATION */
                        0x00078000, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000b, /* EMC_QSAFE */
@@ -939,12 +960,12 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x20820800, /* EMC_XM2DQSPADCTRL3 */
                        0x000c0000, /* EMC_DLL_XFORM_DQ0 */
-                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR0 */
+                       0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR0 */
                        0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR2 */
                        0x00078000, /* EMC_DLL_XFORM_DQS1 */
                        0x00078000, /* EMC_DLL_XFORM_DQS2 */
                        0x00078000, /* EMC_DLL_XFORM_DQS3 */
@@ -962,7 +983,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000000, /* EMC_CDB_CNTL_1 */
                        0x00000004, /* EMC_FBIO_CFG6 */
                        0x00000007, /* EMC_QUSE */
-                       0x00000003, /* EMC_EINPUT */
+                       0x00000004, /* EMC_EINPUT */
                        0x00000005, /* EMC_EINPUT_DURATION */
                        0x00078000, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000b, /* EMC_QSAFE */
@@ -971,12 +992,12 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x20820800, /* EMC_XM2DQSPADCTRL3 */
                        0x000c0000, /* EMC_DLL_XFORM_DQ0 */
-                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR0 */
+                       0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR0 */
                        0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00048000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x000fc000, /* EMC_DLL_XFORM_ADDR2 */
                        0x00078000, /* EMC_DLL_XFORM_DQS1 */
                        0x00078000, /* EMC_DLL_XFORM_DQS2 */
                        0x00078000, /* EMC_DLL_XFORM_DQS3 */
@@ -991,7 +1012,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000000, /* EMC_DLL_XFORM_QUSE3 */
                },
                {
-                       0x00000068, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00000034, /* MC_PTSA_GRANT_DECREMENT */
                        0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */
                        0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */
                        0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */
@@ -1002,8 +1023,12 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+                       0x4E564441, /* System Verification tag */
+                       0x04010600, /* Reg_tool Version */
+                       0x02000100, /* DVFS_tool Version */
+                       102000,     /* SDRAM Frequency */
                },
-               0x00000012, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x00000014, /* EMC_ZCAL_WAIT_CNT after clock change */
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
                0xf320000e, /* EMC_CFG */
                0x00000000, /* Mode Register 0 */
@@ -1013,12 +1038,12 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                6890,       /* expected dvfs latency (ns) */
        },
        {
-               0x41,       /* Rev 4.0.3 */
+               0x42,       /* Rev 4.0.3 */
                204000,     /* SDRAM frequency */
                900,        /* min voltage */
                "pll_p",    /* clock source id */
-               0x40000002, /* CLK_SOURCE_EMC */
-               99,         /* number of burst_regs */
+               0x44000002, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
                30,         /* number of trim_regs (each channel) */
                11,         /* number of up_down_regs */
                {
@@ -1068,10 +1093,10 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0001aa86, /* EMC_FBIO_CFG5 */
                        0x005800a8, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00030000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00050000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00050000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00050000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00050000, /* EMC_DLL_XFORM_DQS7 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE4 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE6 */
@@ -1087,20 +1112,20 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x77ffc004, /* EMC_XM2CLKPADCTRL */
                        0x81f1f008, /* EMC_XM2COMPPADCTRL */
                        0x00000000, /* EMC_XM2VTTGENPADCTRL */
-                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
                        0x0000003f, /* EMC_DSR_VTTGEN_DRV */
                        0x00000000, /* EMC_TXDSRVTTGEN */
                        0x02000100, /* EMC_FBIO_SPARE */
-                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000301, /* EMC_CTT_TERM_CTRL */
                        0x00064000, /* EMC_ZCAL_INTERVAL */
                        0x0000004a, /* EMC_ZCAL_WAIT_CNT */
-                       0x000f000f, /* EMC_MRS_WAIT_CNT */
-                       0x000f000f, /* EMC_MRS_WAIT_CNT2 */
+                       0x00100010, /* EMC_MRS_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
                        0x00000000, /* EMC_CTT */
                        0x00000000, /* EMC_CTT_DURATION */
-                       0x80000714, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
                        0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
                        0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
                        0x01000003, /* MC_EMEM_ARB_CFG */
@@ -1121,6 +1146,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x000a0506, /* MC_EMEM_ARB_DA_COVERS */
                        0x71e40a07, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x0004032c, /* EMC_SEL_DPD_CTRL */
                },
                {
                        0x00000000, /* EMC_CDB_CNTL_1 */
@@ -1128,22 +1154,22 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000008, /* EMC_QUSE */
                        0x00000004, /* EMC_EINPUT */
                        0x00000005, /* EMC_EINPUT_DURATION */
-                       0x00030000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00050000, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000c, /* EMC_QSAFE */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x0000000e, /* EMC_RDV */
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x20820800, /* EMC_XM2DQSPADCTRL3 */
                        0x00058000, /* EMC_DLL_XFORM_DQ0 */
-                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00070000, /* EMC_DLL_XFORM_ADDR0 */
+                       0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x00060000, /* EMC_DLL_XFORM_ADDR0 */
                        0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00070000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00060000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00050000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00050000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00050000, /* EMC_DLL_XFORM_DQS3 */
                        0x00058000, /* EMC_DLL_XFORM_DQ1 */
                        0x00058000, /* EMC_DLL_XFORM_DQ2 */
                        0x00058000, /* EMC_DLL_XFORM_DQ3 */
@@ -1160,22 +1186,22 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000008, /* EMC_QUSE */
                        0x00000004, /* EMC_EINPUT */
                        0x00000005, /* EMC_EINPUT_DURATION */
-                       0x00030000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00050000, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000c, /* EMC_QSAFE */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x0000000e, /* EMC_RDV */
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x20820800, /* EMC_XM2DQSPADCTRL3 */
                        0x00058000, /* EMC_DLL_XFORM_DQ0 */
-                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00070000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x00060000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00070000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00060000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00050000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00050000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00050000, /* EMC_DLL_XFORM_DQS3 */
                        0x00058000, /* EMC_DLL_XFORM_DQ1 */
                        0x00058000, /* EMC_DLL_XFORM_DQ2 */
                        0x00058000, /* EMC_DLL_XFORM_DQ3 */
@@ -1187,7 +1213,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000000, /* EMC_DLL_XFORM_QUSE3 */
                },
                {
-                       0x000000d0, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00000068, /* MC_PTSA_GRANT_DECREMENT */
                        0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */
                        0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */
                        0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */
@@ -1198,6 +1224,10 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */
                        0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+                       0x4E564441, /* System Verification tag */
+                       0x04010600, /* Reg_tool Version */
+                       0x02000100, /* DVFS_tool Version */
+                       204000,     /* SDRAM Frequency */
                },
                0x00000017, /* EMC_ZCAL_WAIT_CNT after clock change */
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
@@ -1209,12 +1239,12 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                3420,       /* expected dvfs latency (ns) */
        },
        {
-               0x41,       /* Rev 4.0.3 */
+               0x42,       /* Rev 4.0.3 */
                312000,     /* SDRAM frequency */
                1000,       /* min voltage */
                "pll_c",    /* clock source id */
                0x24000002, /* CLK_SOURCE_EMC */
-               99,         /* number of burst_regs */
+               100,        /* number of burst_regs */
                30,         /* number of trim_regs (each channel) */
                11,         /* number of up_down_regs */
                {
@@ -1233,21 +1263,21 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000002, /* EMC_REXT */
                        0x00000000, /* EMC_WEXT */
                        0x00000003, /* EMC_WDV */
-                       0x00000003, /* EMC_WDV_MASK */
+                       0x0000000f, /* EMC_WDV_MASK */
                        0x00000006, /* EMC_IBDLY */
                        0x00010000, /* EMC_PUTERM_EXTRA */
                        0x00000000, /* EMC_CDB_CNTL_2 */
                        0x00000004, /* EMC_QRST */
-                       0x0000000f, /* EMC_RDV_MASK */
-                       0x0000049d, /* EMC_REFRESH */
+                       0x00000011, /* EMC_RDV_MASK */
+                       0x0000049b, /* EMC_REFRESH */
                        0x00000000, /* EMC_BURST_REFRESH_NUM */
-                       0x00000127, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000126, /* EMC_PRE_REFRESH_REQ_CNT */
                        0x00000002, /* EMC_PDEX2WR */
                        0x00000002, /* EMC_PDEX2RD */
                        0x00000005, /* EMC_PCHG2PDEN */
                        0x00000000, /* EMC_ACT2PDEN */
                        0x00000001, /* EMC_AR2PDEN */
-                       0x0000000c, /* EMC_RW2PDEN */
+                       0x0000000d, /* EMC_RW2PDEN */
                        0x0000002c, /* EMC_TXSR */
                        0x0000002c, /* EMC_TXSRDLL */
                        0x00000005, /* EMC_TCKE */
@@ -1257,17 +1287,17 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000007, /* EMC_TRPAB */
                        0x00000001, /* EMC_TCLKSTABLE */
                        0x00000003, /* EMC_TCLKSTOP */
-                       0x00000514, /* EMC_TREFBW */
+                       0x00000512, /* EMC_TREFBW */
                        0x00000006, /* EMC_QUSE_EXTRA */
                        0x00000020, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
                        0x0001aa86, /* EMC_FBIO_CFG5 */
                        0x005800a8, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00020000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00020000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00020000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00020000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS7 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE4 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE6 */
@@ -1283,20 +1313,20 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x77ffc004, /* EMC_XM2CLKPADCTRL */
                        0x81f1f008, /* EMC_XM2COMPPADCTRL */
                        0x00000000, /* EMC_XM2VTTGENPADCTRL */
-                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
                        0x0000003f, /* EMC_DSR_VTTGEN_DRV */
                        0x00000000, /* EMC_TXDSRVTTGEN */
                        0x02000100, /* EMC_FBIO_SPARE */
-                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000301, /* EMC_CTT_TERM_CTRL */
                        0x00064000, /* EMC_ZCAL_INTERVAL */
                        0x00000071, /* EMC_ZCAL_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT */
-                       0x000e000e, /* EMC_MRS_WAIT_CNT2 */
+                       0x00100010, /* EMC_MRS_WAIT_CNT */
+                       0x00100010, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
                        0x00000000, /* EMC_CTT */
                        0x00000000, /* EMC_CTT_DURATION */
-                       0x80000a4c, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x80000a48, /* EMC_DYN_SELF_REF_CONTROL */
                        0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
                        0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
                        0x0b000004, /* MC_EMEM_ARB_CFG */
@@ -1317,6 +1347,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x000c0709, /* MC_EMEM_ARB_DA_COVERS */
                        0x71c50f0a, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x0004032c, /* EMC_SEL_DPD_CTRL */
                },
                {
                        0x00000000, /* EMC_CDB_CNTL_1 */
@@ -1324,22 +1355,22 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000009, /* EMC_QUSE */
                        0x00000004, /* EMC_EINPUT */
                        0x00000006, /* EMC_EINPUT_DURATION */
-                       0x00030000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000d, /* EMC_QSAFE */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x0000000f, /* EMC_RDV */
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x20820800, /* EMC_XM2DQSPADCTRL3 */
                        0x00038000, /* EMC_DLL_XFORM_DQ0 */
-                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
                        0x00038000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
                        0x00038000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS3 */
                        0x00038000, /* EMC_DLL_XFORM_DQ1 */
                        0x00038000, /* EMC_DLL_XFORM_DQ2 */
                        0x00038000, /* EMC_DLL_XFORM_DQ3 */
@@ -1356,22 +1387,22 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000009, /* EMC_QUSE */
                        0x00000004, /* EMC_EINPUT */
                        0x00000006, /* EMC_EINPUT_DURATION */
-                       0x00030000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000d, /* EMC_QSAFE */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x0000000f, /* EMC_RDV */
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x20820800, /* EMC_XM2DQSPADCTRL3 */
                        0x00038000, /* EMC_DLL_XFORM_DQ0 */
-                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
                        0x00038000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
                        0x00038000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS3 */
                        0x00038000, /* EMC_DLL_XFORM_DQ1 */
                        0x00038000, /* EMC_DLL_XFORM_DQ2 */
                        0x00038000, /* EMC_DLL_XFORM_DQ3 */
@@ -1383,7 +1414,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000000, /* EMC_DLL_XFORM_QUSE3 */
                },
                {
-                       0x00000140, /* MC_PTSA_GRANT_DECREMENT */
+                       0x000000a0, /* MC_PTSA_GRANT_DECREMENT */
                        0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */
                        0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */
                        0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */
@@ -1394,6 +1425,10 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */
                        0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */
                        0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+                       0x4E564441, /* System Verification tag */
+                       0x04010600, /* Reg_tool Version */
+                       0x02000100, /* DVFS_tool Version */
+                       312000,     /* SDRAM Frequency */
                },
                0x00000021, /* EMC_ZCAL_WAIT_CNT after clock change */
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
@@ -1402,15 +1437,15 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                0x00010083, /* Mode Register 1 */
                0x00020004, /* Mode Register 2 */
                0x000b0000, /* Mode Register 4 */
-               2680,       /* expected dvfs latency (ns) */
+               2180,       /* expected dvfs latency (ns) */
        },
        {
-               0x41,       /* Rev 4.0.3 */
+               0x42,       /* Rev 4.0.3 */
                408000,     /* SDRAM frequency */
                1000,       /* min voltage */
                "pll_p",    /* clock source id */
-               0x40000000, /* CLK_SOURCE_EMC */
-               99,         /* number of burst_regs */
+               0x44000000, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
                30,         /* number of trim_regs (each channel) */
                11,         /* number of up_down_regs */
                {
@@ -1460,10 +1495,10 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0001a886, /* EMC_FBIO_CFG5 */
                        0x00580088, /* EMC_CFG_DIG_DLL */
                        0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
-                       0x00030000, /* EMC_DLL_XFORM_DQS4 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS5 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS6 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS7 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE4 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE5 */
                        0x00000000, /* EMC_DLL_XFORM_QUSE6 */
@@ -1479,20 +1514,20 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x77ffc004, /* EMC_XM2CLKPADCTRL */
                        0x81f1f008, /* EMC_XM2COMPPADCTRL */
                        0x00000000, /* EMC_XM2VTTGENPADCTRL */
-                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
                        0x0000003f, /* EMC_DSR_VTTGEN_DRV */
                        0x00000000, /* EMC_TXDSRVTTGEN */
                        0x02000100, /* EMC_FBIO_SPARE */
-                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000301, /* EMC_CTT_TERM_CTRL */
                        0x00064000, /* EMC_ZCAL_INTERVAL */
                        0x00000093, /* EMC_ZCAL_WAIT_CNT */
-                       0x00110011, /* EMC_MRS_WAIT_CNT */
-                       0x00110011, /* EMC_MRS_WAIT_CNT2 */
+                       0x00120012, /* EMC_MRS_WAIT_CNT */
+                       0x00120012, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
                        0x00000000, /* EMC_CTT */
                        0x00000000, /* EMC_CTT_DURATION */
-                       0x80000d24, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
                        0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
                        0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
                        0x02000006, /* MC_EMEM_ARB_CFG */
@@ -1513,6 +1548,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0010090c, /* MC_EMEM_ARB_DA_COVERS */
                        0x71c7130d, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x0004032c, /* EMC_SEL_DPD_CTRL */
                },
                {
                        0x00000000, /* EMC_CDB_CNTL_1 */
@@ -1520,22 +1556,22 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0000000b, /* EMC_QUSE */
                        0x00000006, /* EMC_EINPUT */
                        0x00000006, /* EMC_EINPUT_DURATION */
-                       0x00030000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000e, /* EMC_QSAFE */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x00000011, /* EMC_RDV */
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
-                       0x10410421, /* EMC_XM2DQSPADCTRL3 */
+                       0x1c71c721, /* EMC_XM2DQSPADCTRL3 */
                        0x00020000, /* EMC_DLL_XFORM_DQ0 */
-                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00018000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x00020000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00018000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00020000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS3 */
                        0x00020000, /* EMC_DLL_XFORM_DQ1 */
                        0x00020000, /* EMC_DLL_XFORM_DQ2 */
                        0x00020000, /* EMC_DLL_XFORM_DQ3 */
@@ -1552,22 +1588,22 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0000000b, /* EMC_QUSE */
                        0x00000006, /* EMC_EINPUT */
                        0x00000006, /* EMC_EINPUT_DURATION */
-                       0x00030000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS0 */
                        0x0000000e, /* EMC_QSAFE */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x00000011, /* EMC_RDV */
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
-                       0x10410421, /* EMC_XM2DQSPADCTRL3 */
+                       0x1c71c721, /* EMC_XM2DQSPADCTRL3 */
                        0x00020000, /* EMC_DLL_XFORM_DQ0 */
-                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00018000, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00000000, /* EMC_XM2CLKPADCTRL2 */
+                       0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x00020000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00018000, /* EMC_DLL_XFORM_ADDR2 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS1 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS2 */
-                       0x00030000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00020000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00028000, /* EMC_DLL_XFORM_DQS3 */
                        0x00020000, /* EMC_DLL_XFORM_DQ1 */
                        0x00020000, /* EMC_DLL_XFORM_DQ2 */
                        0x00020000, /* EMC_DLL_XFORM_DQ3 */
@@ -1590,6 +1626,10 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */
                        0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */
                        0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+                       0x4E564441, /* System Verification tag */
+                       0x04010600, /* Reg_tool Version */
+                       0x02000100, /* DVFS_tool Version */
+                       408000,     /* SDRAM Frequency */
                },
                0x00000029, /* EMC_ZCAL_WAIT_CNT after clock change */
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
@@ -1601,12 +1641,12 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                1750,       /* expected dvfs latency (ns) */
        },
        {
-               0x41,       /* Rev 4.0.3 */
+               0x42,       /* Rev 4.0.3 */
                624000,     /* SDRAM frequency */
                1100,       /* min voltage */
                "pll_c",    /* clock source id */
                0x24000000, /* CLK_SOURCE_EMC */
-               99,         /* number of burst_regs */
+               100,        /* number of burst_regs */
                30,         /* number of trim_regs (each channel) */
                11,         /* number of up_down_regs */
                {
@@ -1631,9 +1671,9 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000000, /* EMC_CDB_CNTL_2 */
                        0x00000007, /* EMC_QRST */
                        0x00000017, /* EMC_RDV_MASK */
-                       0x00000945, /* EMC_REFRESH */
+                       0x00000941, /* EMC_REFRESH */
                        0x00000000, /* EMC_BURST_REFRESH_NUM */
-                       0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000250, /* EMC_PRE_REFRESH_REQ_CNT */
                        0x00000004, /* EMC_PDEX2WR */
                        0x00000004, /* EMC_PDEX2RD */
                        0x0000000b, /* EMC_PCHG2PDEN */
@@ -1649,7 +1689,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0000000e, /* EMC_TRPAB */
                        0x00000001, /* EMC_TCLKSTABLE */
                        0x00000003, /* EMC_TCLKSTOP */
-                       0x00000a28, /* EMC_TREFBW */
+                       0x00000a24, /* EMC_TREFBW */
                        0x0000000b, /* EMC_QUSE_EXTRA */
                        0x00000020, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
@@ -1688,7 +1728,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
                        0x00000000, /* EMC_CTT */
                        0x00000000, /* EMC_CTT_DURATION */
-                       0x80001395, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x8000138d, /* EMC_DYN_SELF_REF_CONTROL */
                        0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
                        0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
                        0x06000009, /* MC_EMEM_ARB_CFG */
@@ -1709,6 +1749,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00160e13, /* MC_EMEM_ARB_DA_COVERS */
                        0x71ca1d14, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x0004032c, /* EMC_SEL_DPD_CTRL */
                },
                {
                        0x00000000, /* EMC_CDB_CNTL_1 */
@@ -1722,19 +1763,19 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000015, /* EMC_RDV */
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x18618621, /* EMC_XM2DQSPADCTRL3 */
-                       0x00003010, /* EMC_DLL_XFORM_DQ0 */
-                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00000010, /* EMC_DLL_XFORM_ADDR0 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x0000000e, /* EMC_DLL_XFORM_ADDR0 */
                        0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00000010, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0000000e, /* EMC_DLL_XFORM_ADDR2 */
                        0x0000000a, /* EMC_DLL_XFORM_DQS1 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS2 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS3 */
-                       0x00003010, /* EMC_DLL_XFORM_DQ1 */
-                       0x00003010, /* EMC_DLL_XFORM_DQ2 */
-                       0x00003010, /* EMC_DLL_XFORM_DQ3 */
+                       0x0000400a, /* EMC_DLL_XFORM_DQS2 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQS3 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQ3 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
@@ -1755,15 +1796,15 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x18618621, /* EMC_XM2DQSPADCTRL3 */
                        0x0000000a, /* EMC_DLL_XFORM_DQ0 */
-                       0xa8f10000, /* EMC_AUTO_CAL_CONFIG */
-                       0x00000010, /* EMC_DLL_XFORM_ADDR0 */
+                       0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x0000000e, /* EMC_DLL_XFORM_ADDR0 */
                        0x00000909, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00000010, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0000000e, /* EMC_DLL_XFORM_ADDR2 */
                        0x0000000a, /* EMC_DLL_XFORM_DQS1 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS2 */
-                       0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+                       0x0000400a, /* EMC_DLL_XFORM_DQS2 */
+                       0x0000000b, /* EMC_DLL_XFORM_DQS3 */
                        0x0000000a, /* EMC_DLL_XFORM_DQ1 */
                        0x0000000a, /* EMC_DLL_XFORM_DQ2 */
                        0x0000000a, /* EMC_DLL_XFORM_DQ3 */
@@ -1786,6 +1827,10 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */
                        0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */
                        0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+                       0x4E564441, /* System Verification tag */
+                       0x04010600, /* Reg_tool Version */
+                       0x02000100, /* DVFS_tool Version */
+                       624000,     /* SDRAM Frequency */
                },
                0x0000003d, /* EMC_ZCAL_WAIT_CNT after clock change */
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
@@ -1794,24 +1839,24 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                0x00010003, /* Mode Register 1 */
                0x00020018, /* Mode Register 2 */
                0x000b0000, /* Mode Register 4 */
-               1440,       /* expected dvfs latency (ns) */
+               1230,       /* expected dvfs latency (ns) */
        },
        {
-               0x41,       /* Rev 4.0.3 */
+               0x42,       /* Rev 4.0.3 */
                744000,     /* SDRAM frequency */
                1100,       /* min voltage */
                "pll_m",    /* clock source id */
-               0x80000000, /* CLK_SOURCE_EMC */
-               99,         /* number of burst_regs */
+               0x84000000, /* CLK_SOURCE_EMC */
+               100,        /* number of burst_regs */
                30,         /* number of trim_regs (each channel) */
                11,         /* number of up_down_regs */
                {
                        0x0000002c, /* EMC_RC */
-                       0x00000061, /* EMC_RFC */
+                       0x00000060, /* EMC_RFC */
                        0x00000000, /* EMC_RFC_SLR */
                        0x0000001f, /* EMC_RAS */
                        0x0000000d, /* EMC_RP */
-                       0x0000000f, /* EMC_R2W */
+                       0x00000010, /* EMC_R2W */
                        0x0000000d, /* EMC_W2R */
                        0x00000005, /* EMC_R2P */
                        0x00000013, /* EMC_W2P */
@@ -1827,9 +1872,9 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000000, /* EMC_CDB_CNTL_2 */
                        0x00000009, /* EMC_QRST */
                        0x0000001a, /* EMC_RDV_MASK */
-                       0x00000b1e, /* EMC_REFRESH */
+                       0x00000b15, /* EMC_REFRESH */
                        0x00000000, /* EMC_BURST_REFRESH_NUM */
-                       0x000002c7, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x000002c5, /* EMC_PRE_REFRESH_REQ_CNT */
                        0x00000005, /* EMC_PDEX2WR */
                        0x00000005, /* EMC_PDEX2RD */
                        0x0000000d, /* EMC_PCHG2PDEN */
@@ -1845,7 +1890,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000010, /* EMC_TRPAB */
                        0x00000001, /* EMC_TCLKSTABLE */
                        0x00000003, /* EMC_TCLKSTOP */
-                       0x00000c21, /* EMC_TREFBW */
+                       0x00000c18, /* EMC_TREFBW */
                        0x0000010d, /* EMC_QUSE_EXTRA */
                        0x00000020, /* EMC_ODT_WRITE */
                        0x00000000, /* EMC_ODT_READ */
@@ -1869,7 +1914,7 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0000003d, /* EMC_XM2DQSPADCTRL2 */
                        0x00000000, /* EMC_XM2DQPADCTRL2 */
                        0x77ffc004, /* EMC_XM2CLKPADCTRL */
-                       0x81f1f408, /* EMC_XM2COMPPADCTRL */
+                       0x81f1f008, /* EMC_XM2COMPPADCTRL */
                        0x00000000, /* EMC_XM2VTTGENPADCTRL */
                        0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
                        0x0000003f, /* EMC_DSR_VTTGEN_DRV */
@@ -1878,13 +1923,13 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000301, /* EMC_CTT_TERM_CTRL */
                        0x00064000, /* EMC_ZCAL_INTERVAL */
                        0x0000010c, /* EMC_ZCAL_WAIT_CNT */
-                       0x00150015, /* EMC_MRS_WAIT_CNT */
-                       0x00150015, /* EMC_MRS_WAIT_CNT2 */
+                       0x00160016, /* EMC_MRS_WAIT_CNT */
+                       0x00160016, /* EMC_MRS_WAIT_CNT2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
                        0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
                        0x00000000, /* EMC_CTT */
                        0x00000000, /* EMC_CTT_DURATION */
-                       0x8000172f, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x8000171e, /* EMC_DYN_SELF_REF_CONTROL */
                        0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */
                        0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */
                        0x0300000b, /* MC_EMEM_ARB_CFG */
@@ -1903,8 +1948,9 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
                        0x08090103, /* MC_EMEM_ARB_DA_TURNS */
                        0x00191016, /* MC_EMEM_ARB_DA_COVERS */
-                       0x71cc2217, /* MC_EMEM_ARB_MISC0 */
+                       0x71ac2217, /* MC_EMEM_ARB_MISC0 */
                        0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0x0004000c, /* EMC_SEL_DPD_CTRL */
                },
                {
                        0x00000000, /* EMC_CDB_CNTL_1 */
@@ -1913,21 +1959,21 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0000000b, /* EMC_EINPUT */
                        0x00000007, /* EMC_EINPUT_DURATION */
                        0x0000000a, /* EMC_DLL_XFORM_DQS0 */
-                       0x00000011, /* EMC_QSAFE */
+                       0x00000010, /* EMC_QSAFE */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x00000018, /* EMC_RDV */
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x18618621, /* EMC_XM2DQSPADCTRL3 */
                        0x00008007, /* EMC_DLL_XFORM_DQ0 */
                        0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
-                       0x00004009, /* EMC_DLL_XFORM_ADDR0 */
+                       0x0000400a, /* EMC_DLL_XFORM_ADDR0 */
                        0x00000707, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00004009, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0000400a, /* EMC_DLL_XFORM_ADDR2 */
                        0x0000400a, /* EMC_DLL_XFORM_DQS1 */
-                       0x0000800a, /* EMC_DLL_XFORM_DQS2 */
-                       0x0000400a, /* EMC_DLL_XFORM_DQS3 */
+                       0x0000400a, /* EMC_DLL_XFORM_DQS2 */
+                       0x00004009, /* EMC_DLL_XFORM_DQS3 */
                        0x00008007, /* EMC_DLL_XFORM_DQ1 */
                        0x00008007, /* EMC_DLL_XFORM_DQ2 */
                        0x00008007, /* EMC_DLL_XFORM_DQ3 */
@@ -1945,21 +1991,21 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x0000000b, /* EMC_EINPUT */
                        0x00000007, /* EMC_EINPUT_DURATION */
                        0x0000000a, /* EMC_DLL_XFORM_DQS0 */
-                       0x00000011, /* EMC_QSAFE */
+                       0x00000010, /* EMC_QSAFE */
                        0x00000000, /* EMC_DLL_XFORM_QUSE0 */
                        0x00000018, /* EMC_RDV */
                        0x00249249, /* EMC_XM2DQSPADCTRL4 */
                        0x18618621, /* EMC_XM2DQSPADCTRL3 */
                        0x00008007, /* EMC_DLL_XFORM_DQ0 */
                        0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
-                       0x00004009, /* EMC_DLL_XFORM_ADDR0 */
-                       0x00000909, /* EMC_XM2CLKPADCTRL2 */
+                       0x0000400a, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000707, /* EMC_XM2CLKPADCTRL2 */
                        0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
                        0x00000000, /* EMC_DLL_XFORM_ADDR1 */
-                       0x00004009, /* EMC_DLL_XFORM_ADDR2 */
+                       0x0000400a, /* EMC_DLL_XFORM_ADDR2 */
                        0x0000400a, /* EMC_DLL_XFORM_DQS1 */
-                       0x0000800a, /* EMC_DLL_XFORM_DQS2 */
-                       0x0000400a, /* EMC_DLL_XFORM_DQS3 */
+                       0x0000400a, /* EMC_DLL_XFORM_DQS2 */
+                       0x00004009, /* EMC_DLL_XFORM_DQS3 */
                        0x00008007, /* EMC_DLL_XFORM_DQ1 */
                        0x00008007, /* EMC_DLL_XFORM_DQ2 */
                        0x00008007, /* EMC_DLL_XFORM_DQ3 */
@@ -1982,15 +2028,19 @@ static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = {
                        0x00110011, /* MC_LATENCY_ALLOWANCE_NV3 */
                        0x00740036, /* MC_LATENCY_ALLOWANCE_EPP_0 */
                        0x00740074, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+                       0x4E564441, /* System Verification tag */
+                       0x04010600, /* Reg_tool Version */
+                       0x02000100, /* DVFS_tool Version */
+                       744000,     /* SDRAM Frequency */
                },
-               0x00000048, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x00000047, /* EMC_ZCAL_WAIT_CNT after clock change */
                0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
                0xf3200000, /* EMC_CFG */
                0x00000000, /* Mode Register 0 */
                0x00010043, /* Mode Register 1 */
                0x0002001a, /* Mode Register 2 */
                0x000b0000, /* Mode Register 4 */
-               1200,       /* expected dvfs latency (ns) */
+               1230,       /* expected dvfs latency (ns) */
        },
 };
 
@@ -4374,8 +4424,9 @@ static struct tegra11_emc_pdata e1580_A01P_AP40_pdata = {
 
 static struct tegra11_emc_pdata e1580_A01P_AP40_2gb_pdata = {
        .description = "e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb",
-       .tables = e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table,
-       .num_tables = ARRAY_SIZE(e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table),
+
+       .tables = e1580_fa164a1ma_gd_f_table,
+       .num_tables = ARRAY_SIZE(e1580_fa164a1ma_gd_f_table),
 };
 
 static struct tegra11_emc_pdata *pluto_get_emc_data(void)