ARM: tegra20: pm: flush L1 data before exit coherency
Prashant Gaikwad [Tue, 27 Mar 2012 12:10:35 +0000 (17:10 +0530)]
Bug 934368

Change-Id: I960d8ae5c6390e719b8ee6c9cbc067cf8d28122d
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/92543
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>

arch/arm/mach-tegra/sleep-t2.S

index fc7b3db..b205565 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/include/mach/sleep-t2.S
  *
- * Copyright (c) 2010-2011, NVIDIA Corporation.
+ * Copyright (c) 2010-2012, NVIDIA Corporation.
  * Copyright (c) 2011, Google, Inc.
  *
  * Author: Colin Cross <ccross@android.com>
@@ -201,6 +201,16 @@ ENTRY(tegra2_sleep_wfi)
 
 tegra_sleep_cpu_save_finish:
        mrc     p15, 0, r11, c1, c0, 1  @ save actlr before exiting coherency
+
+       dsb
+#ifdef MULTI_CACHE
+       mov32   r10, cpu_cache
+       mov     lr, pc
+       ldr     pc, [r10, #CACHE_FLUSH_KERN_ALL]
+#else
+       bl      __cpuc_flush_kern_all
+#endif
+
        bl      tegra_cpu_exit_coherency
 
        mov32   r0, TEGRA_PMC_VIRT + PMC_SCRATCH41