arm: tegra: bypass PllP during LP1 suspend
Bo Yan [Thu, 31 Oct 2013 17:43:31 +0000 (10:43 -0700)]
RAM repair requires PllP, so it shouldn't be disabled. To save
power, instead of keeping it running at 408Mhz, enable bypass
mode, so RAM repair logic can be clocked by oscillator. This
is done when LP1 entry is from fast cluster only.

In addition, change PLLP_OUT0_RATIO to 0 so the reshift clock
is not being further divided down, change it back to default
value after PllP is enabled and bypass is disabled.

bug 1373419

Change-Id: I2bbcd15eaa0b222faadcae00448bd677c8387c69
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/310133
(cherry picked from commit 5eeb5fac5efde9f99c2bf2524570f4231359af5a)
Reviewed-on: http://git-master/r/328858
Reviewed-by: Harry Hong <hhong@nvidia.com>
Tested-by: Harry Hong <hhong@nvidia.com>

arch/arm/mach-tegra/sleep-t3.S

index b7558ff..6eb6080 100644 (file)
 #define CLK_RESET_PLLA_BASE            0xb0
 #define CLK_RESET_PLLX_BASE            0xe0
 
+#define CLK_RESET_PLLP_RESHIFT         0x528
+#define CLK_RESET_PLLP_RESHIFT_DEFAULT 0x3b
+#define CLK_RESET_PLLP_RESHIFT_ENABLE  0x3
+
 #define CLK_RESET_PLLC_MISC            0x8c
 #define CLK_RESET_PLLM_MISC            0x9c
 #define CLK_RESET_PLLP_MISC            0xac
 #define CLK_RESET_CLK_ENB_W_CLR                0x44c
 #endif
 
+
 #define I2C_CNFG       0x0
 #define I2C_ADDR0      0x4
 #define I2C_DATA1      0xc
 
 #define MSELECT_CLKM                   (0x3 << 30)
 
+#define FLOW_CONTROL_CLUSTER_CONTROL   0x2c
+
 #if USE_PLL_LOCK_BITS
 #define LOCK_DELAY             PLL_POST_LOCK_DELAY
 #else
@@ -483,6 +490,15 @@ ENTRY(tegra3_lp1_reset)
        pll_locked r1, r0, CLK_RESET_PLLC_BASE
        pll_locked r1, r0, CLK_RESET_PLLX_BASE
 
+#if !defined(CONFIG_ARCH_TEGRA_3x_SOC)
+       ldr     r1, [r0, #CLK_RESET_PLLP_BASE]
+       bic     r1, r1, #(1<<31)                /* disable PllP bypass */
+       str     r1, [r0, #CLK_RESET_PLLP_BASE]
+
+       mov     r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT
+       str     r1, [r0, #CLK_RESET_PLLP_RESHIFT]
+#endif
+
        mov32   r7, TEGRA_TMRUS_BASE
        ldr     r1, [r7]
        add     r1, r1, #LOCK_DELAY
@@ -809,16 +825,25 @@ lp1_clocks_prepare:
        ldr     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
        bic     r0, r0, #(1 << 12)
        str     r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
-       b       powerdown_pll_pcx
 
-powerdown_pll_pcx:
        ldr     r11, [r4, #PMC_SCRATCH37]       @ load the LP1 flags
        tst     r11, #TEGRA_POWER_LP1_AUDIO     @ check if voice call is going on
        bne     powerdown_pll_cx                @ if yes, do not turn off pll-p/pll-a
 
+       ldr     r0, [r6, #FLOW_CONTROL_CLUSTER_CONTROL]
+       tst     r0, #1
        ldr     r0, [r5, #CLK_RESET_PLLP_BASE]
        bic     r0, r0, #(1<<30)
+#if !defined(CONFIG_ARCH_TEGRA_3x_SOC)
+       orreq   r0, r0, #(1<<31)                @ enable PllP bypass on fast
+#endif
        str     r0, [r5, #CLK_RESET_PLLP_BASE]
+
+#if !defined(CONFIG_ARCH_TEGRA_3x_SOC)
+       mov     r0, #CLK_RESET_PLLP_RESHIFT_ENABLE
+       str     r0, [r5, #CLK_RESET_PLLP_RESHIFT]
+#endif
+
        ldr     r0, [r5, #CLK_RESET_PLLA_BASE]
        bic     r0, r0, #(1<<30)
        str     r0, [r5, #CLK_RESET_PLLA_BASE]