Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
John W. Linville [Mon, 13 Dec 2010 20:20:45 +0000 (15:20 -0500)]
1  2 
MAINTAINERS
drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

diff --combined MAINTAINERS
@@@ -161,7 -161,7 +161,7 @@@ M: Greg Kroah-Hartman <gregkh@suse.de
  L:    linux-serial@vger.kernel.org
  W:    http://serial.sourceforge.net
  S:    Maintained
 -T:    quilt kernel.org/pub/linux/kernel/people/gregkh/gregkh-2.6/
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty-2.6.git
  F:    drivers/serial/8250*
  F:    include/linux/serial_8250.h
  
@@@ -1080,6 -1080,12 +1080,12 @@@ S:    Supporte
  F:    Documentation/aoe/
  F:    drivers/block/aoe/
  
+ ATHEROS ATH GENERIC UTILITIES
+ M:    "Luis R. Rodriguez" <lrodriguez@atheros.com>
+ L:    linux-wireless@vger.kernel.org
+ S:    Supported
+ F:    drivers/net/wireless/ath/*
  ATHEROS ATH5K WIRELESS DRIVER
  M:    Jiri Slaby <jirislaby@gmail.com>
  M:    Nick Kossifidis <mickflemm@gmail.com>
@@@ -1359,7 -1365,7 +1365,7 @@@ F:      include/net/bluetooth
  
  BONDING DRIVER
  M:    Jay Vosburgh <fubar@us.ibm.com>
 -L:    bonding-devel@lists.sourceforge.net
 +L:    netdev@vger.kernel.org
  W:    http://sourceforge.net/projects/bonding/
  S:    Supported
  F:    drivers/net/bonding/
@@@ -1829,13 -1835,6 +1835,13 @@@ W:    http://www.chelsio.co
  S:    Supported
  F:    drivers/net/cxgb4vf/
  
 +STMMAC ETHERNET DRIVER
 +M:    Giuseppe Cavallaro <peppe.cavallaro@st.com>
 +L:    netdev@vger.kernel.org
 +W:    http://www.stlinux.com
 +S:    Supported
 +F:    drivers/net/stmmac/
 +
  CYBERPRO FB DRIVER
  M:    Russell King <linux@arm.linux.org.uk>
  L:    linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@@ -3115,8 -3114,6 +3121,8 @@@ M:      Alex Duyck <alexander.h.duyck@intel.
  M:    John Ronciak <john.ronciak@intel.com>
  L:    e1000-devel@lists.sourceforge.net
  W:    http://e1000.sourceforge.net/
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-2.6.git
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next-2.6.git
  S:    Supported
  F:    Documentation/networking/e100.txt
  F:    Documentation/networking/e1000.txt
@@@ -5685,7 -5682,7 +5691,7 @@@ S:      Maintaine
  
  STAGING SUBSYSTEM
  M:    Greg Kroah-Hartman <gregkh@suse.de>
 -T:    git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-next-2.6.git
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6.git
  L:    devel@driverdev.osuosl.org
  S:    Maintained
  F:    drivers/staging/
@@@ -5919,7 -5916,7 +5925,7 @@@ S:      Maintaine
  TTY LAYER
  M:    Greg Kroah-Hartman <gregkh@suse.de>
  S:    Maintained
 -T:    quilt kernel.org/pub/linux/kernel/people/gregkh/gregkh-2.6/
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty-2.6.git
  F:    drivers/char/tty_*
  F:    drivers/serial/serial_core.c
  F:    include/linux/serial_core.h
@@@ -6242,7 -6239,7 +6248,7 @@@ USB SUBSYSTE
  M:    Greg Kroah-Hartman <gregkh@suse.de>
  L:    linux-usb@vger.kernel.org
  W:    http://www.linux-usb.org
 -T:    quilt kernel.org/pub/linux/kernel/people/gregkh/gregkh-2.6/
 +T:    git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb-2.6.git
  S:    Supported
  F:    Documentation/usb/
  F:    drivers/net/usb/
@@@ -6607,14 -6604,14 +6613,14 @@@ F:   drivers/platform/x8
  
  XEN PCI SUBSYSTEM
  M:    Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
 -L:    xen-devel@lists.xensource.com
 +L:    xen-devel@lists.xensource.com (moderated for non-subscribers)
  S:    Supported
  F:    arch/x86/pci/*xen*
  F:    drivers/pci/*xen*
  
  XEN SWIOTLB SUBSYSTEM
  M:    Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
 -L:    xen-devel@lists.xensource.com
 +L:    xen-devel@lists.xensource.com (moderated for non-subscribers)
  S:    Supported
  F:    arch/x86/xen/*swiotlb*
  F:    drivers/xen/*swiotlb*
  XEN HYPERVISOR INTERFACE
  M:    Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
  M:    Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
 -L:    xen-devel@lists.xen.org
 +L:    xen-devel@lists.xensource.com (moderated for non-subscribers)
  L:    virtualization@lists.osdl.org
  S:    Supported
  F:    arch/x86/xen/
@@@ -62,7 -62,6 +62,7 @@@
  static int ar9003_hw_power_interpolate(int32_t x,
                                       int32_t *px, int32_t *py, u_int16_t np);
  
 +
  static const struct ar9300_eeprom ar9300_default = {
        .eepromVersion = 2,
        .templateVersion = 2,
@@@ -3035,6 -3034,8 +3035,8 @@@ static u32 ath9k_hw_ar9300_get_eeprom(s
                return !!(pBase->featureEnable & BIT(5));
        case EEP_CHAIN_MASK_REDUCE:
                return (pBase->miscConfiguration >> 0x3) & 0x1;
+       case EEP_ANT_DIV_CTL1:
+               return le32_to_cpu(eep->base_ext1.ant_div_control);
        default:
                return 0;
        }
@@@ -3073,8 -3074,8 +3075,8 @@@ static bool ar9300_read_eeprom(struct a
        int i;
  
        if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
-               ath_print(common, ATH_DBG_EEPROM,
-                         "eeprom address not in range\n");
+               ath_dbg(common, ATH_DBG_EEPROM,
+                       "eeprom address not in range\n");
                return false;
        }
  
        return true;
  
  error:
-       ath_print(common, ATH_DBG_EEPROM,
-                 "unable to read eeprom region at offset %d\n", address);
+       ath_dbg(common, ATH_DBG_EEPROM,
+               "unable to read eeprom region at offset %d\n", address);
        return false;
  }
  
@@@ -3190,17 -3191,15 +3192,15 @@@ static bool ar9300_uncompress_block(str
                length &= 0xff;
  
                if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
-                       ath_print(common, ATH_DBG_EEPROM,
-                                 "Restore at %d: spot=%d "
-                                 "offset=%d length=%d\n",
-                                  it, spot, offset, length);
+                       ath_dbg(common, ATH_DBG_EEPROM,
+                               "Restore at %d: spot=%d offset=%d length=%d\n",
+                               it, spot, offset, length);
                        memcpy(&mptr[spot], &block[it+2], length);
                        spot += length;
                } else if (length > 0) {
-                       ath_print(common, ATH_DBG_EEPROM,
-                                 "Bad restore at %d: spot=%d "
-                                 "offset=%d length=%d\n",
-                                 it, spot, offset, length);
+                       ath_dbg(common, ATH_DBG_EEPROM,
+                               "Bad restore at %d: spot=%d offset=%d length=%d\n",
+                               it, spot, offset, length);
                        return false;
                }
        }
@@@ -3221,14 -3220,15 +3221,15 @@@ static int ar9300_compress_decision(str
        switch (code) {
        case _CompressNone:
                if (length != mdata_size) {
-                       ath_print(common, ATH_DBG_EEPROM,
-                                 "EEPROM structure size mismatch"
-                                 "memory=%d eeprom=%d\n", mdata_size, length);
+                       ath_dbg(common, ATH_DBG_EEPROM,
+                               "EEPROM structure size mismatch memory=%d eeprom=%d\n",
+                               mdata_size, length);
                        return -1;
                }
                memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
-               ath_print(common, ATH_DBG_EEPROM, "restored eeprom %d:"
-                         " uncompressed, length %d\n", it, length);
+               ath_dbg(common, ATH_DBG_EEPROM,
+                       "restored eeprom %d: uncompressed, length %d\n",
+                       it, length);
                break;
        case _CompressBlock:
                if (reference == 0) {
                } else {
                        eep = ar9003_eeprom_struct_find_by_id(reference);
                        if (eep == NULL) {
-                               ath_print(common, ATH_DBG_EEPROM,
-                                         "cant find reference eeprom"
-                                         "struct %d\n", reference);
+                               ath_dbg(common, ATH_DBG_EEPROM,
+                                       "cant find reference eeprom struct %d\n",
+                                       reference);
                                return -1;
                        }
                        memcpy(mptr, eep, mdata_size);
                }
-               ath_print(common, ATH_DBG_EEPROM,
-                         "restore eeprom %d: block, reference %d,"
-                         " length %d\n", it, reference, length);
+               ath_dbg(common, ATH_DBG_EEPROM,
+                       "restore eeprom %d: block, reference %d, length %d\n",
+                       it, reference, length);
                ar9300_uncompress_block(ah, mptr, mdata_size,
                                        (u8 *) (word + COMP_HDR_LEN), length);
                break;
        default:
-               ath_print(common, ATH_DBG_EEPROM, "unknown compression"
-                         " code %d\n", code);
+               ath_dbg(common, ATH_DBG_EEPROM,
+                       "unknown compression code %d\n", code);
                return -1;
        }
        return 0;
@@@ -3321,27 -3321,30 +3322,30 @@@ static int ar9300_eeprom_restore_intern
        memcpy(mptr, &ar9300_default, mdata_size);
  
        read = ar9300_read_eeprom;
-       cptr = AR9300_BASE_ADDR;
-       ath_print(common, ATH_DBG_EEPROM,
+       if (AR_SREV_9485(ah))
+               cptr = AR9300_BASE_ADDR_4K;
+       else
+               cptr = AR9300_BASE_ADDR;
+       ath_dbg(common, ATH_DBG_EEPROM,
                "Trying EEPROM accesss at Address 0x%04x\n", cptr);
        if (ar9300_check_eeprom_header(ah, read, cptr))
                goto found;
  
        cptr = AR9300_BASE_ADDR_512;
-       ath_print(common, ATH_DBG_EEPROM,
+       ath_dbg(common, ATH_DBG_EEPROM,
                "Trying EEPROM accesss at Address 0x%04x\n", cptr);
        if (ar9300_check_eeprom_header(ah, read, cptr))
                goto found;
  
        read = ar9300_read_otp;
        cptr = AR9300_BASE_ADDR;
-       ath_print(common, ATH_DBG_EEPROM,
+       ath_dbg(common, ATH_DBG_EEPROM,
                "Trying OTP accesss at Address 0x%04x\n", cptr);
        if (ar9300_check_eeprom_header(ah, read, cptr))
                goto found;
  
        cptr = AR9300_BASE_ADDR_512;
-       ath_print(common, ATH_DBG_EEPROM,
+       ath_dbg(common, ATH_DBG_EEPROM,
                "Trying OTP accesss at Address 0x%04x\n", cptr);
        if (ar9300_check_eeprom_header(ah, read, cptr))
                goto found;
        goto fail;
  
  found:
-       ath_print(common, ATH_DBG_EEPROM, "Found valid EEPROM data");
+       ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n");
  
        for (it = 0; it < MSTATE; it++) {
                if (!read(ah, cptr, word, COMP_HDR_LEN))
  
                ar9300_comp_hdr_unpack(word, &code, &reference,
                                       &length, &major, &minor);
-               ath_print(common, ATH_DBG_EEPROM,
-                         "Found block at %x: code=%d ref=%d"
-                         "length=%d major=%d minor=%d\n", cptr, code,
-                         reference, length, major, minor);
-               if (length >= 1024) {
-                       ath_print(common, ATH_DBG_EEPROM,
-                                 "Skipping bad header\n");
+               ath_dbg(common, ATH_DBG_EEPROM,
+                       "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
+                       cptr, code, reference, length, major, minor);
+               if ((!AR_SREV_9485(ah) && length >= 1024) ||
+                   (AR_SREV_9485(ah) && length >= (4 * 1024))) {
+                       ath_dbg(common, ATH_DBG_EEPROM,
+                               "Skipping bad header\n");
                        cptr -= COMP_HDR_LEN;
                        continue;
                }
                checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
                mchecksum = word[COMP_HDR_LEN + osize] |
                    (word[COMP_HDR_LEN + osize + 1] << 8);
-               ath_print(common, ATH_DBG_EEPROM,
-                         "checksum %x %x\n", checksum, mchecksum);
+               ath_dbg(common, ATH_DBG_EEPROM,
+                       "checksum %x %x\n", checksum, mchecksum);
                if (checksum == mchecksum) {
                        ar9300_compress_decision(ah, it, code, reference, mptr,
                                                 word, length, mdata_size);
                } else {
-                       ath_print(common, ATH_DBG_EEPROM,
-                                 "skipping block with bad checksum\n");
+                       ath_dbg(common, ATH_DBG_EEPROM,
+                               "skipping block with bad checksum\n");
                }
                cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
        }
@@@ -3449,9 -3452,15 +3453,15 @@@ static s32 ar9003_hw_xpa_bias_level_get
  static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
  {
        int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
-       REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
-       REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB, bias >> 2);
-       REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
+       if (AR_SREV_9485(ah))
+               REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
+       else {
+               REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
+               REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB,
+                             bias >> 2);
+               REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
+       }
  }
  
  static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
@@@ -3506,11 -3515,25 +3516,25 @@@ static void ar9003_hw_ant_ctrl_apply(st
        value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
        REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
  
-       value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
-       REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value);
+       if (!AR_SREV_9485(ah)) {
+               value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
+               REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL,
+                             value);
+               value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
+               REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL,
+                             value);
+       }
  
-       value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
-       REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value);
+       if (AR_SREV_9485(ah)) {
+               value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
+               REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_CTRL_ALL,
+                             value);
+               REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE,
+                             value >> 6);
+               REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE,
+                             value >> 7);
+       }
  }
  
  static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
@@@ -3630,28 -3653,101 +3654,101 @@@ static void ar9003_hw_atten_apply(struc
        }
  }
  
+ static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
+ {
+       int timeout = 100;
+       while (pmu_set != REG_READ(ah, pmu_reg)) {
+               if (timeout-- == 0)
+                       return false;
+               REG_WRITE(ah, pmu_reg, pmu_set);
+               udelay(10);
+       }
+       return true;
+ }
  static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
  {
        int internal_regulator =
                ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
  
        if (internal_regulator) {
-               /* Internal regulator is ON. Write swreg register. */
-               int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
-               REG_WRITE(ah, AR_RTC_REG_CONTROL1,
-               REG_READ(ah, AR_RTC_REG_CONTROL1) &
-                        (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
-               REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
-               /* Set REG_CONTROL1.SWREG_PROGRAM */
-               REG_WRITE(ah, AR_RTC_REG_CONTROL1,
-                         REG_READ(ah,
-                                  AR_RTC_REG_CONTROL1) |
-                                  AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
+               if (AR_SREV_9485(ah)) {
+                       int reg_pmu_set;
+                       reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
+                       REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
+                       if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
+                               return;
+                       reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) |
+                                     (7 << 14) | (6 << 17) | (1 << 20) |
+                                     (3 << 24) | (1 << 28);
+                       REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
+                       if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
+                               return;
+                       reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
+                                       | (4 << 26);
+                       REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
+                       if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
+                               return;
+                       reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
+                                       | (1 << 21);
+                       REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
+                       if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
+                               return;
+               } else {
+                       /* Internal regulator is ON. Write swreg register. */
+                       int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
+                       REG_WRITE(ah, AR_RTC_REG_CONTROL1,
+                                 REG_READ(ah, AR_RTC_REG_CONTROL1) &
+                                 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
+                       REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
+                       /* Set REG_CONTROL1.SWREG_PROGRAM */
+                       REG_WRITE(ah, AR_RTC_REG_CONTROL1,
+                                 REG_READ(ah,
+                                          AR_RTC_REG_CONTROL1) |
+                                          AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
+               }
        } else {
-               REG_WRITE(ah, AR_RTC_SLEEP_CLK,
-                         (REG_READ(ah,
-                                   AR_RTC_SLEEP_CLK) |
-                                   AR_RTC_FORCE_SWREG_PRD));
+               if (AR_SREV_9485(ah)) {
+                       REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
+                       while (REG_READ_FIELD(ah, AR_PHY_PMU2,
+                                             AR_PHY_PMU2_PGM))
+                               udelay(10);
+                       REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
+                       while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
+                                              AR_PHY_PMU1_PWD))
+                               udelay(10);
+                       REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
+                       while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
+                                             AR_PHY_PMU2_PGM))
+                               udelay(10);
+               } else
+                       REG_WRITE(ah, AR_RTC_SLEEP_CLK,
+                                 (REG_READ(ah,
+                                  AR_RTC_SLEEP_CLK) |
+                                  AR_RTC_FORCE_SWREG_PRD));
+       }
+ }
+ static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
+ {
+       struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+       u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
+       if (eep->baseEepHeader.featureEnable & 0x40) {
+               tuning_caps_param &= 0x7f;
+               REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
+                             tuning_caps_param);
+               REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
+                             tuning_caps_param);
        }
  }
  
@@@ -3663,6 -3759,8 +3760,8 @@@ static void ath9k_hw_ar9300_set_board_v
        ar9003_hw_drive_strength_apply(ah);
        ar9003_hw_atten_apply(ah, chan);
        ar9003_hw_internal_regulator_apply(ah);
+       if (AR_SREV_9485(ah))
+               ar9003_hw_apply_tuning_caps(ah);
  }
  
  static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
@@@ -4092,22 -4190,9 +4191,9 @@@ static void ar9003_hw_set_target_power_
            ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
                                              is2GHz) + ht40PowerIncForPdadc;
  
-       while (i < ar9300RateSize) {
-               ath_print(common, ATH_DBG_EEPROM,
-                         "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-               i++;
-               ath_print(common, ATH_DBG_EEPROM,
-                         "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-               i++;
-               ath_print(common, ATH_DBG_EEPROM,
-                         "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-               i++;
-               ath_print(common, ATH_DBG_EEPROM,
-                         "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
-               i++;
+       for (i = 0; i < ar9300RateSize; i++) {
+               ath_dbg(common, ATH_DBG_EEPROM,
+                       "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
        }
  }
  
@@@ -4126,18 -4211,17 +4212,17 @@@ static int ar9003_hw_cal_pier_get(struc
        struct ath_common *common = ath9k_hw_common(ah);
  
        if (ichain >= AR9300_MAX_CHAINS) {
-               ath_print(common, ATH_DBG_EEPROM,
-                         "Invalid chain index, must be less than %d\n",
-                         AR9300_MAX_CHAINS);
+               ath_dbg(common, ATH_DBG_EEPROM,
+                       "Invalid chain index, must be less than %d\n",
+                       AR9300_MAX_CHAINS);
                return -1;
        }
  
        if (mode) {             /* 5GHz */
                if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
-                       ath_print(common, ATH_DBG_EEPROM,
-                                 "Invalid 5GHz cal pier index, must "
-                                 "be less than %d\n",
-                                 AR9300_NUM_5G_CAL_PIERS);
+                       ath_dbg(common, ATH_DBG_EEPROM,
+                               "Invalid 5GHz cal pier index, must be less than %d\n",
+                               AR9300_NUM_5G_CAL_PIERS);
                        return -1;
                }
                pCalPier = &(eep->calFreqPier5G[ipier]);
                is2GHz = 0;
        } else {
                if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
-                       ath_print(common, ATH_DBG_EEPROM,
-                                 "Invalid 2GHz cal pier index, must "
-                                 "be less than %d\n", AR9300_NUM_2G_CAL_PIERS);
+                       ath_dbg(common, ATH_DBG_EEPROM,
+                               "Invalid 2GHz cal pier index, must be less than %d\n",
+                               AR9300_NUM_2G_CAL_PIERS);
                        return -1;
                }
  
@@@ -4176,23 -4260,27 +4261,27 @@@ static int ar9003_hw_power_control_over
        REG_RMW(ah, AR_PHY_TPC_11_B0,
                (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
                AR_PHY_TPC_OLPC_GAIN_DELTA);
-       REG_RMW(ah, AR_PHY_TPC_11_B1,
-               (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
-               AR_PHY_TPC_OLPC_GAIN_DELTA);
-       REG_RMW(ah, AR_PHY_TPC_11_B2,
-               (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
-               AR_PHY_TPC_OLPC_GAIN_DELTA);
+       if (ah->caps.tx_chainmask & BIT(1))
+               REG_RMW(ah, AR_PHY_TPC_11_B1,
+                       (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
+                       AR_PHY_TPC_OLPC_GAIN_DELTA);
+       if (ah->caps.tx_chainmask & BIT(2))
+               REG_RMW(ah, AR_PHY_TPC_11_B2,
+                       (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
+                       AR_PHY_TPC_OLPC_GAIN_DELTA);
  
        /* enable open loop power control on chip */
        REG_RMW(ah, AR_PHY_TPC_6_B0,
                (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
                AR_PHY_TPC_6_ERROR_EST_MODE);
-       REG_RMW(ah, AR_PHY_TPC_6_B1,
-               (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
-               AR_PHY_TPC_6_ERROR_EST_MODE);
-       REG_RMW(ah, AR_PHY_TPC_6_B2,
-               (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
-               AR_PHY_TPC_6_ERROR_EST_MODE);
+       if (ah->caps.tx_chainmask & BIT(1))
+               REG_RMW(ah, AR_PHY_TPC_6_B1,
+                       (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
+                       AR_PHY_TPC_6_ERROR_EST_MODE);
+       if (ah->caps.tx_chainmask & BIT(2))
+               REG_RMW(ah, AR_PHY_TPC_6_B2,
+                       (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
+                       AR_PHY_TPC_6_ERROR_EST_MODE);
  
        /*
         * enable temperature compensation
@@@ -4297,11 -4385,11 +4386,11 @@@ static int ar9003_hw_calibration_apply(
  
        /* interpolate  */
        for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
-               ath_print(common, ATH_DBG_EEPROM,
-                         "ch=%d f=%d low=%d %d h=%d %d\n",
-                         ichain, frequency, lfrequency[ichain],
-                         lcorrection[ichain], hfrequency[ichain],
-                         hcorrection[ichain]);
+               ath_dbg(common, ATH_DBG_EEPROM,
+                       "ch=%d f=%d low=%d %d h=%d %d\n",
+                       ichain, frequency, lfrequency[ichain],
+                       lcorrection[ichain], hfrequency[ichain],
+                       hcorrection[ichain]);
                /* they're the same, so just pick one */
                if (hfrequency[ichain] == lfrequency[ichain]) {
                        correction[ichain] = lcorrection[ichain];
        ar9003_hw_power_control_override(ah, frequency, correction, voltage,
                                         temperature);
  
-       ath_print(common, ATH_DBG_EEPROM,
-                 "for frequency=%d, calibration correction = %d %d %d\n",
-                 frequency, correction[0], correction[1], correction[2]);
+       ath_dbg(common, ATH_DBG_EEPROM,
+               "for frequency=%d, calibration correction = %d %d %d\n",
+               frequency, correction[0], correction[1], correction[2]);
  
        return 0;
  }
@@@ -4560,11 -4648,10 +4649,10 @@@ static void ar9003_hw_set_power_per_rat
                else
                        freq = centers.ctl_center;
  
-               ath_print(common, ATH_DBG_REGULATORY,
-                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
-                         "EXT_ADDITIVE %d\n",
-                         ctlMode, numCtlModes, isHt40CtlMode,
-                         (pCtlMode[ctlMode] & EXT_ADDITIVE));
+               ath_dbg(common, ATH_DBG_REGULATORY,
+                       "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
+                       ctlMode, numCtlModes, isHt40CtlMode,
+                       (pCtlMode[ctlMode] & EXT_ADDITIVE));
  
                /* walk through each CTL index stored in EEPROM */
                if (is2ghz) {
                }
  
                for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
-                       ath_print(common, ATH_DBG_REGULATORY,
-                                 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
-                                 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
-                                 "chan %dn",
-                                 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
-                                 chan->channel);
+                       ath_dbg(common, ATH_DBG_REGULATORY,
+                               "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
+                               i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
+                               chan->channel);
  
                                /*
                                 * compare test group from regulatory
  
                        minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
  
-                       ath_print(common, ATH_DBG_REGULATORY,
-                                 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d "
-                                 "sP %d minCtlPwr %d\n",
-                                 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
-                                 scaledPower, minCtlPower);
+                       ath_dbg(common, ATH_DBG_REGULATORY,
+                               "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
+                               ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
+                               scaledPower, minCtlPower);
  
                        /* Apply ctl mode to correct target power set */
                        switch (pCtlMode[ctlMode]) {
@@@ -4699,18 -4783,8 +4784,8 @@@ static void ath9k_hw_ar9300_set_txpower
                return;
  
        for (i = 0; i < ar9300RateSize; i++) {
-               ath_print(common, ATH_DBG_EEPROM,
-                         "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-               i++;
-               ath_print(common, ATH_DBG_EEPROM,
-                         "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-               i++;
-               ath_print(common, ATH_DBG_EEPROM,
-                         "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-               i++;
-               ath_print(common, ATH_DBG_EEPROM,
-                         "TPC[%02d] 0x%08x\n\n", i, targetPowerValT2[i]);
-               i++;
+               ath_dbg(common, ATH_DBG_EEPROM,
+                       "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
        }
  
        /*
@@@ -4758,6 -4832,16 +4833,16 @@@ s32 ar9003_hw_get_rx_gain_idx(struct at
        return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
  }
  
+ u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
+ {
+       struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+       if (is_2ghz)
+               return eep->modalHeader2G.spurChans;
+       else
+               return eep->modalHeader5G.spurChans;
+ }
  const struct eeprom_ops eep_ar9300_ops = {
        .check_eeprom = ath9k_hw_ar9300_check_eeprom,
        .get_eeprom = ath9k_hw_ar9300_get_eeprom,