video: tegra: dc: disable disp.emc clock when 0 new rate is requested
Nitin Kumbhar [Wed, 14 Mar 2012 14:10:38 +0000 (19:10 +0530)]
Not disabling emc clock when it's being set to zero results in incorrect
reference count when a call is made to clear bandwidth. This happens when
two worker threads try to handle dc emc rate. A deep-sleep/wake-up cycle
easily shows this scenario.

With this fix, disp.emc's ref count is properly managed even after multiple
deep-sleep/wake-up cycles.

Bug 947228

Change-Id: I045fafbd483af1e3d492b8d0395275e45642d059
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/90100
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

drivers/video/tegra/dc/dc.c

index 080438b..ac024f6 100644 (file)
@@ -993,8 +993,12 @@ static void tegra_dc_program_bandwidth(struct tegra_dc *dc)
                /* going from 0 to non-zero */
                if (!dc->emc_clk_rate && !tegra_is_clk_enabled(dc->emc_clk))
                        clk_enable(dc->emc_clk);
+
                dc->emc_clk_rate = dc->new_emc_clk_rate;
                clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
+
+               if (!dc->new_emc_clk_rate) /* going from non-zero to 0 */
+                       clk_disable(dc->emc_clk);
        }
 
        for (i = 0; i < DC_N_WINDOWS; i++) {