serial: tegra: Add delay after TX DMA complete
Pradeep Goudagunta [Thu, 4 Aug 2011 06:04:12 +0000 (11:04 +0530)]
Add 30 micro seconds delay after TX DMA burst complete, to make
sure DMA burst completed before writing to tx fifo.

Bug 847599

Original-Change-Id: Ifcc1f3f208f8c2396ef410bedfa1158643b94015
Reviewed-on: http://git-master/r/44933
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Tested-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R16d2c723f934b72ee770795d988c8ef9659c55e2

drivers/tty/serial/tegra_hsuart.c

index caec27f..ba855c5 100644 (file)
@@ -479,6 +479,7 @@ static void tegra_tx_dma_complete_callback(struct tegra_dma_req *req)
        unsigned long flags;
 
        dev_vdbg(t->uport.dev, "%s: %d\n", __func__, count);
+       udelay(30);
 
        spin_lock_irqsave(&t->uport.lock, flags);
        xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);