drm/radeon/kms: AGP systems need PCI bus mastering enabled
Dave Airlie [Thu, 5 Nov 2009 05:36:53 +0000 (15:36 +1000)]
We might not hit this yet, but when if we do any sort of writeback
we really need to enable PCI bus mastering on these systems from
what I can see.

This enables PCI BM on all radeons that require it.

Signed-off-by: Dave Airlie <airlied@redhat.com>

drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/r300.c
drivers/gpu/drm/radeon/r420.c
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/rs400.c

index c9e93ea..4e0a804 100644 (file)
@@ -94,6 +94,15 @@ int r100_pci_gart_init(struct radeon_device *rdev)
        return radeon_gart_table_ram_alloc(rdev);
 }
 
+/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
+void r100_enable_bm(struct radeon_device *rdev)
+{
+       uint32_t tmp;
+       /* Enable bus mastering */
+       tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
+       WREG32(RADEON_BUS_CNTL, tmp);
+}
+
 int r100_pci_gart_enable(struct radeon_device *rdev)
 {
        uint32_t tmp;
@@ -105,9 +114,6 @@ int r100_pci_gart_enable(struct radeon_device *rdev)
        WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
        tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
        WREG32(RADEON_AIC_HI_ADDR, tmp);
-       /* Enable bus mastering */
-       tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
-       WREG32(RADEON_BUS_CNTL, tmp);
        /* set PCI GART page-table base address */
        WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
        tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
@@ -3108,6 +3114,7 @@ static int r100_startup(struct radeon_device *rdev)
        r100_gpu_init(rdev);
        /* Initialize GART (initialize after TTM so we can allocate
         * memory through TTM but finalize after TTM) */
+       r100_enable_bm(rdev);
        if (rdev->flags & RADEON_IS_PCI) {
                r = r100_pci_gart_enable(rdev);
                if (r)
index 2f43ee8..9a57985 100644 (file)
@@ -1193,6 +1193,12 @@ static int r300_startup(struct radeon_device *rdev)
                if (r)
                        return r;
        }
+
+       if (rdev->family == CHIP_R300 ||
+           rdev->family == CHIP_R350 ||
+           rdev->family == CHIP_RV350)
+               r100_enable_bm(rdev);
+
        if (rdev->flags & RADEON_IS_PCI) {
                r = r100_pci_gart_enable(rdev);
                if (r)
index 1cefdbc..e7e4f5a 100644 (file)
@@ -335,6 +335,9 @@ int r420_init(struct radeon_device *rdev)
        if (r) {
                return r;
        }
+       if (rdev->family == CHIP_R420)
+               r100_enable_bm(rdev);
+
        if (rdev->flags & RADEON_IS_PCIE) {
                r = rv370_pcie_gart_init(rdev);
                if (r)
index 224506a..9cb81a8 100644 (file)
@@ -1029,6 +1029,7 @@ extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
                                struct radeon_cs_packet *pkt,
                                unsigned idx);
+extern void r100_enable_bm(struct radeon_device *rdev);
 
 /* rv200,rv250,rv280 */
 extern void r200_set_safe_registers(struct radeon_device *rdev);
index ca03716..f1de558 100644 (file)
@@ -387,6 +387,7 @@ static int rs400_startup(struct radeon_device *rdev)
        r300_clock_startup(rdev);
        /* Initialize GPU configuration (# pipes, ...) */
        rs400_gpu_init(rdev);
+       r100_enable_bm(rdev);
        /* Initialize GART (initialize after TTM so we can allocate
         * memory through TTM but finalize after TTM) */
        r = rs400_gart_enable(rdev);