ASoC: Tegra: Complete Tegra->Tegra20 renaming
Stephen Warren [Tue, 26 Jul 2011 22:21:08 +0000 (16:21 -0600)]
Rename Tegra20-specific Kconfig variables, module filenames, all internal
symbol names, clocks, and platform devices, to reflect the fact the DAS
and I2S drivers are for a specific HW version.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

Rebase-Id: Re5b72edd9dff4c93466b2db96dd40eb708343ccb

sound/soc/tegra/Kconfig
sound/soc/tegra/Makefile
sound/soc/tegra/tegra20_das.c
sound/soc/tegra/tegra20_das.h
sound/soc/tegra/tegra20_i2s.c
sound/soc/tegra/tegra20_i2s.h
sound/soc/tegra/tegra_wm8903.c

index 5894869..9f740d7 100644 (file)
@@ -5,14 +5,14 @@ config SND_SOC_TEGRA
        help
          Say Y or M here if you want support for SoC audio on Tegra.
 
-config SND_SOC_TEGRA_DAS
-       tristate "Tegra Digital Audio Switch driver"
+config SND_SOC_TEGRA20_DAS
+       tristate "Tegra 20 Digital Audio Switch driver"
        depends on SND_SOC_TEGRA && ARCH_TEGRA_2x_SOC
 
-config SND_SOC_TEGRA_I2S
-       tristate "Tegra I2S driver"
+config SND_SOC_TEGRA20_I2S
+       tristate "Tegra 20 I2S driver"
        depends on SND_SOC_TEGRA && ARCH_TEGRA_2x_SOC
-       select SND_SOC_TEGRA_DAS
+       select SND_SOC_TEGRA20_DAS
        help
          Say Y or M if you want to add support for codecs attached to the
          Tegra I2S interface. You will also need to select the individual
@@ -38,7 +38,7 @@ config SND_SOC_TEGRA_WM8903
        tristate "SoC Audio support for Tegra boards using a WM8903 codec"
        depends on SND_SOC_TEGRA && I2C
        depends on MACH_HAS_SND_SOC_TEGRA_WM8903
-       select SND_SOC_TEGRA_I2S if ARCH_TEGRA_2x_SOC
+       select SND_SOC_TEGRA20_I2S if ARCH_TEGRA_2x_SOC
        select SND_SOC_WM8903
        help
          Say Y or M here if you want to add support for SoC audio on Tegra
index c0f0a56..8e1f883 100644 (file)
@@ -1,14 +1,14 @@
 # Tegra platform Support
-snd-soc-tegra-das-objs := tegra20_das.o
+snd-soc-tegra20-das-objs := tegra20_das.o
 snd-soc-tegra-pcm-objs := tegra_pcm.o
-snd-soc-tegra-i2s-objs := tegra20_i2s.o
+snd-soc-tegra20-i2s-objs := tegra20_i2s.o
 snd-soc-tegra-spdif-objs := tegra_spdif.o
 snd-soc-tegra-utils-objs += tegra_asoc_utils.o
 
 obj-$(CONFIG_SND_SOC_TEGRA) += snd-soc-tegra-utils.o
-obj-$(CONFIG_SND_SOC_TEGRA_DAS) += snd-soc-tegra-das.o
+obj-$(CONFIG_SND_SOC_TEGRA20_DAS) += snd-soc-tegra20-das.o
 obj-$(CONFIG_SND_SOC_TEGRA) += snd-soc-tegra-pcm.o
-obj-$(CONFIG_SND_SOC_TEGRA_I2S) += snd-soc-tegra-i2s.o
+obj-$(CONFIG_SND_SOC_TEGRA20_I2S) += snd-soc-tegra20-i2s.o
 obj-$(CONFIG_SND_SOC_TEGRA_SPDIF) += snd-soc-tegra-spdif.o
 
 # Tegra machine Support
index f20457d..b647798 100644 (file)
 #include <sound/soc.h>
 #include "tegra20_das.h"
 
-#define DRV_NAME "tegra-das"
+#define DRV_NAME "tegra20-das"
 
-static struct tegra_das *das;
+static struct tegra20_das *das;
 
-static inline void tegra_das_write(u32 reg, u32 val)
+static inline void tegra20_das_write(u32 reg, u32 val)
 {
        __raw_writel(val, das->regs + reg);
 }
 
-static inline u32 tegra_das_read(u32 reg)
+static inline u32 tegra20_das_read(u32 reg)
 {
        return __raw_readl(das->regs + reg);
 }
 
-int tegra_das_connect_dap_to_dac(int dap, int dac)
+int tegra20_das_connect_dap_to_dac(int dap, int dac)
 {
        u32 addr;
        u32 reg;
@@ -53,17 +53,17 @@ int tegra_das_connect_dap_to_dac(int dap, int dac)
        if (!das)
                return -ENODEV;
 
-       addr = TEGRA_DAS_DAP_CTRL_SEL +
-               (dap * TEGRA_DAS_DAP_CTRL_SEL_STRIDE);
-       reg = dac << TEGRA_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P;
+       addr = TEGRA20_DAS_DAP_CTRL_SEL +
+               (dap * TEGRA20_DAS_DAP_CTRL_SEL_STRIDE);
+       reg = dac << TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P;
 
-       tegra_das_write(addr, reg);
+       tegra20_das_write(addr, reg);
 
        return 0;
 }
-EXPORT_SYMBOL_GPL(tegra_das_connect_dap_to_dac);
+EXPORT_SYMBOL_GPL(tegra20_das_connect_dap_to_dac);
 
-int tegra_das_connect_dap_to_dap(int dap, int otherdap, int master,
+int tegra20_das_connect_dap_to_dap(int dap, int otherdap, int master,
                                        int sdata1rx, int sdata2rx)
 {
        u32 addr;
@@ -72,20 +72,20 @@ int tegra_das_connect_dap_to_dap(int dap, int otherdap, int master,
        if (!das)
                return -ENODEV;
 
-       addr = TEGRA_DAS_DAP_CTRL_SEL +
-               (dap * TEGRA_DAS_DAP_CTRL_SEL_STRIDE);
-       reg = otherdap << TEGRA_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P |
-               !!sdata2rx << TEGRA_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P |
-               !!sdata1rx << TEGRA_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P |
-               !!master << TEGRA_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P;
+       addr = TEGRA20_DAS_DAP_CTRL_SEL +
+               (dap * TEGRA20_DAS_DAP_CTRL_SEL_STRIDE);
+       reg = otherdap << TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P |
+               !!sdata2rx << TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P |
+               !!sdata1rx << TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P |
+               !!master << TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P;
 
-       tegra_das_write(addr, reg);
+       tegra20_das_write(addr, reg);
 
        return 0;
 }
-EXPORT_SYMBOL_GPL(tegra_das_connect_dap_to_dap);
+EXPORT_SYMBOL_GPL(tegra20_das_connect_dap_to_dap);
 
-int tegra_das_connect_dac_to_dap(int dac, int dap)
+int tegra20_das_connect_dac_to_dap(int dac, int dap)
 {
        u32 addr;
        u32 reg;
@@ -93,78 +93,78 @@ int tegra_das_connect_dac_to_dap(int dac, int dap)
        if (!das)
                return -ENODEV;
 
-       addr = TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL +
-               (dac * TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE);
-       reg = dap << TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P |
-               dap << TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P |
-               dap << TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P;
+       addr = TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL +
+               (dac * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE);
+       reg = dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P |
+               dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P |
+               dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P;
 
-       tegra_das_write(addr, reg);
+       tegra20_das_write(addr, reg);
 
        return 0;
 }
-EXPORT_SYMBOL_GPL(tegra_das_connect_dac_to_dap);
+EXPORT_SYMBOL_GPL(tegra20_das_connect_dac_to_dap);
 
 #ifdef CONFIG_DEBUG_FS
-static int tegra_das_show(struct seq_file *s, void *unused)
+static int tegra20_das_show(struct seq_file *s, void *unused)
 {
        int i;
        u32 addr;
        u32 reg;
 
-       for (i = 0; i < TEGRA_DAS_DAP_CTRL_SEL_COUNT; i++) {
-               addr = TEGRA_DAS_DAP_CTRL_SEL +
-                       (i * TEGRA_DAS_DAP_CTRL_SEL_STRIDE);
-               reg = tegra_das_read(addr);
-               seq_printf(s, "TEGRA_DAS_DAP_CTRL_SEL[%d] = %08x\n", i, reg);
+       for (i = 0; i < TEGRA20_DAS_DAP_CTRL_SEL_COUNT; i++) {
+               addr = TEGRA20_DAS_DAP_CTRL_SEL +
+                       (i * TEGRA20_DAS_DAP_CTRL_SEL_STRIDE);
+               reg = tegra20_das_read(addr);
+               seq_printf(s, "TEGRA20_DAS_DAP_CTRL_SEL[%d] = %08x\n", i, reg);
        }
 
-       for (i = 0; i < TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT; i++) {
-               addr = TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL +
-                       (i * TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE);
-               reg = tegra_das_read(addr);
-               seq_printf(s, "TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL[%d] = %08x\n",
+       for (i = 0; i < TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT; i++) {
+               addr = TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL +
+                       (i * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE);
+               reg = tegra20_das_read(addr);
+               seq_printf(s, "TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL[%d] = %08x\n",
                                 i, reg);
        }
 
        return 0;
 }
 
-static int tegra_das_debug_open(struct inode *inode, struct file *file)
+static int tegra20_das_debug_open(struct inode *inode, struct file *file)
 {
-       return single_open(file, tegra_das_show, inode->i_private);
+       return single_open(file, tegra20_das_show, inode->i_private);
 }
 
-static const struct file_operations tegra_das_debug_fops = {
-       .open    = tegra_das_debug_open,
+static const struct file_operations tegra20_das_debug_fops = {
+       .open    = tegra20_das_debug_open,
        .read    = seq_read,
        .llseek  = seq_lseek,
        .release = single_release,
 };
 
-static void tegra_das_debug_add(struct tegra_das *das)
+static void tegra20_das_debug_add(struct tegra20_das *das)
 {
        das->debug = debugfs_create_file(DRV_NAME, S_IRUGO,
                                         snd_soc_debugfs_root, das,
-                                        &tegra_das_debug_fops);
+                                        &tegra20_das_debug_fops);
 }
 
-static void tegra_das_debug_remove(struct tegra_das *das)
+static void tegra20_das_debug_remove(struct tegra20_das *das)
 {
        if (das->debug)
                debugfs_remove(das->debug);
 }
 #else
-static inline void tegra_das_debug_add(struct tegra_das *das)
+static inline void tegra20_das_debug_add(struct tegra20_das *das)
 {
 }
 
-static inline void tegra_das_debug_remove(struct tegra_das *das)
+static inline void tegra20_das_debug_remove(struct tegra20_das *das)
 {
 }
 #endif
 
-static int __devinit tegra_das_probe(struct platform_device *pdev)
+static int __devinit tegra20_das_probe(struct platform_device *pdev)
 {
        struct resource *res, *region;
        int ret = 0;
@@ -172,9 +172,9 @@ static int __devinit tegra_das_probe(struct platform_device *pdev)
        if (das)
                return -ENODEV;
 
-       das = kzalloc(sizeof(struct tegra_das), GFP_KERNEL);
+       das = kzalloc(sizeof(struct tegra20_das), GFP_KERNEL);
        if (!das) {
-               dev_err(&pdev->dev, "Can't allocate tegra_das\n");
+               dev_err(&pdev->dev, "Can't allocate tegra20_das\n");
                ret = -ENOMEM;
                goto exit;
        }
@@ -202,7 +202,7 @@ static int __devinit tegra_das_probe(struct platform_device *pdev)
                goto err_release;
        }
 
-       tegra_das_debug_add(das);
+       tegra20_das_debug_add(das);
 
        platform_set_drvdata(pdev, das);
 
@@ -217,7 +217,7 @@ exit:
        return ret;
 }
 
-static int __devexit tegra_das_remove(struct platform_device *pdev)
+static int __devexit tegra20_das_remove(struct platform_device *pdev)
 {
        struct resource *res;
 
@@ -226,7 +226,7 @@ static int __devexit tegra_das_remove(struct platform_device *pdev)
 
        platform_set_drvdata(pdev, NULL);
 
-       tegra_das_debug_remove(das);
+       tegra20_das_debug_remove(das);
 
        iounmap(das->regs);
 
@@ -239,25 +239,25 @@ static int __devexit tegra_das_remove(struct platform_device *pdev)
        return 0;
 }
 
-static struct platform_driver tegra_das_driver = {
-       .probe = tegra_das_probe,
-       .remove = __devexit_p(tegra_das_remove),
+static struct platform_driver tegra20_das_driver = {
+       .probe = tegra20_das_probe,
+       .remove = __devexit_p(tegra20_das_remove),
        .driver = {
                .name = DRV_NAME,
        },
 };
 
-static int __init tegra_das_modinit(void)
+static int __init tegra20_das_modinit(void)
 {
-       return platform_driver_register(&tegra_das_driver);
+       return platform_driver_register(&tegra20_das_driver);
 }
-module_init(tegra_das_modinit);
+module_init(tegra20_das_modinit);
 
-static void __exit tegra_das_modexit(void)
+static void __exit tegra20_das_modexit(void)
 {
-       platform_driver_unregister(&tegra_das_driver);
+       platform_driver_unregister(&tegra20_das_driver);
 }
-module_exit(tegra_das_modexit);
+module_exit(tegra20_das_modexit);
 
 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
 MODULE_DESCRIPTION("Tegra DAS driver");
index 5b18c57..2fd731b 100644 (file)
  *
  */
 
-#ifndef __TEGRA_DAS_H__
-#define __TEGRA_DAS_H__
+#ifndef __TEGRA20_DAS_H__
+#define __TEGRA20_DAS_H__
 
-/* Register TEGRA_DAS_DAP_CTRL_SEL */
-#define TEGRA_DAS_DAP_CTRL_SEL                         0x00
-#define TEGRA_DAS_DAP_CTRL_SEL_COUNT                   5
-#define TEGRA_DAS_DAP_CTRL_SEL_STRIDE                  4
-#define TEGRA_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P            31
-#define TEGRA_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S            1
-#define TEGRA_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P      30
-#define TEGRA_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S      1
-#define TEGRA_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P      29
-#define TEGRA_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S      1
-#define TEGRA_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P          0
-#define TEGRA_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S          5
+/* Register TEGRA20_DAS_DAP_CTRL_SEL */
+#define TEGRA20_DAS_DAP_CTRL_SEL                       0x00
+#define TEGRA20_DAS_DAP_CTRL_SEL_COUNT                 5
+#define TEGRA20_DAS_DAP_CTRL_SEL_STRIDE                        4
+#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P          31
+#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S          1
+#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P    30
+#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S    1
+#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P    29
+#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S    1
+#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P                0
+#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S                5
 
-/* Values for field TEGRA_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL */
-#define TEGRA_DAS_DAP_SEL_DAC1 0
-#define TEGRA_DAS_DAP_SEL_DAC2 1
-#define TEGRA_DAS_DAP_SEL_DAC3 2
-#define TEGRA_DAS_DAP_SEL_DAP1 16
-#define TEGRA_DAS_DAP_SEL_DAP2 17
-#define TEGRA_DAS_DAP_SEL_DAP3 18
-#define TEGRA_DAS_DAP_SEL_DAP4 19
-#define TEGRA_DAS_DAP_SEL_DAP5 20
+/* Values for field TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL */
+#define TEGRA20_DAS_DAP_SEL_DAC1       0
+#define TEGRA20_DAS_DAP_SEL_DAC2       1
+#define TEGRA20_DAS_DAP_SEL_DAC3       2
+#define TEGRA20_DAS_DAP_SEL_DAP1       16
+#define TEGRA20_DAS_DAP_SEL_DAP2       17
+#define TEGRA20_DAS_DAP_SEL_DAP3       18
+#define TEGRA20_DAS_DAP_SEL_DAP4       19
+#define TEGRA20_DAS_DAP_SEL_DAP5       20
 
-/* Register TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL */
-#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL                       0x40
-#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT                 3
-#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE                        4
-#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P      28
-#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S      4
-#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P      24
-#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S      4
-#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P         0
-#define TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S         4
+/* Register TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL */
+#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL                     0x40
+#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT               3
+#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE              4
+#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P    28
+#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S    4
+#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P    24
+#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S    4
+#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P       0
+#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S       4
 
 /*
  * Values for:
- * TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL
- * TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL
- * TEGRA_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL
+ * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL
+ * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL
+ * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL
  */
-#define TEGRA_DAS_DAC_SEL_DAP1 0
-#define TEGRA_DAS_DAC_SEL_DAP2 1
-#define TEGRA_DAS_DAC_SEL_DAP3 2
-#define TEGRA_DAS_DAC_SEL_DAP4 3
-#define TEGRA_DAS_DAC_SEL_DAP5 4
+#define TEGRA20_DAS_DAC_SEL_DAP1       0
+#define TEGRA20_DAS_DAC_SEL_DAP2       1
+#define TEGRA20_DAS_DAC_SEL_DAP3       2
+#define TEGRA20_DAS_DAC_SEL_DAP4       3
+#define TEGRA20_DAS_DAC_SEL_DAP5       4
 
 /*
  * Names/IDs of the DACs/DAPs.
  */
 
-#define TEGRA_DAS_DAP_ID_1 0
-#define TEGRA_DAS_DAP_ID_2 1
-#define TEGRA_DAS_DAP_ID_3 2
-#define TEGRA_DAS_DAP_ID_4 3
-#define TEGRA_DAS_DAP_ID_5 4
+#define TEGRA20_DAS_DAP_ID_1 0
+#define TEGRA20_DAS_DAP_ID_2 1
+#define TEGRA20_DAS_DAP_ID_3 2
+#define TEGRA20_DAS_DAP_ID_4 3
+#define TEGRA20_DAS_DAP_ID_5 4
 
-#define TEGRA_DAS_DAC_ID_1 0
-#define TEGRA_DAS_DAC_ID_2 1
-#define TEGRA_DAS_DAC_ID_3 2
+#define TEGRA20_DAS_DAC_ID_1 0
+#define TEGRA20_DAS_DAC_ID_2 1
+#define TEGRA20_DAS_DAC_ID_3 2
 
-struct tegra_das {
+struct tegra20_das {
        struct device *dev;
        void __iomem *regs;
        struct dentry *debug;
@@ -107,29 +107,29 @@ struct tegra_das {
 
 /*
  * Connect a DAP to to a DAC
- * dap_id: DAP to connect: TEGRA_DAS_DAP_ID_*
- * dac_sel: DAC to connect to: TEGRA_DAS_DAP_SEL_DAC*
+ * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
+ * dac_sel: DAC to connect to: TEGRA20_DAS_DAP_SEL_DAC*
  */
-extern int tegra_das_connect_dap_to_dac(int dap_id, int dac_sel);
+extern int tegra20_das_connect_dap_to_dac(int dap_id, int dac_sel);
 
 /*
  * Connect a DAP to to another DAP
- * dap_id: DAP to connect: TEGRA_DAS_DAP_ID_*
- * other_dap_sel: DAP to connect to: TEGRA_DAS_DAP_SEL_DAP*
+ * dap_id: DAP to connect: TEGRA20_DAS_DAP_ID_*
+ * other_dap_sel: DAP to connect to: TEGRA20_DAS_DAP_SEL_DAP*
  * master: Is this DAP the master (1) or slave (0)
  * sdata1rx: Is this DAP's SDATA1 pin RX (1) or TX (0)
  * sdata2rx: Is this DAP's SDATA2 pin RX (1) or TX (0)
  */
-extern int tegra_das_connect_dap_to_dap(int dap_id, int other_dap_sel,
+extern int tegra20_das_connect_dap_to_dap(int dap_id, int other_dap_sel,
                                        int master, int sdata1rx,
                                        int sdata2rx);
 
 /*
  * Connect a DAC's input to a DAP
  * (DAC outputs are selected by the DAP)
- * dac_id: DAC ID to connect: TEGRA_DAS_DAC_ID_*
- * dap_sel: DAP to receive input from: TEGRA_DAS_DAC_SEL_DAP*
+ * dac_id: DAC ID to connect: TEGRA20_DAS_DAC_ID_*
+ * dap_sel: DAP to receive input from: TEGRA20_DAS_DAC_SEL_DAP*
  */
-extern int tegra_das_connect_dac_to_dap(int dac_id, int dap_sel);
+extern int tegra20_das_connect_dac_to_dap(int dac_id, int dap_sel);
 
 #endif
index 7571912..38116a7 100644 (file)
 #include "tegra20_das.h"
 #include "tegra20_i2s.h"
 
-#define DRV_NAME "tegra-i2s"
+#define DRV_NAME "tegra20-i2s"
 
-static inline void tegra_i2s_write(struct tegra_i2s *i2s, u32 reg, u32 val)
+static inline void tegra20_i2s_write(struct tegra20_i2s *i2s, u32 reg, u32 val)
 {
        __raw_writel(val, i2s->regs + reg);
 }
 
-static inline u32 tegra_i2s_read(struct tegra_i2s *i2s, u32 reg)
+static inline u32 tegra20_i2s_read(struct tegra20_i2s *i2s, u32 reg)
 {
        return __raw_readl(i2s->regs + reg);
 }
 
-static void tegra_i2s_inc_clock_ref(struct tegra_i2s *i2s)
+static void tegra20_i2s_inc_clock_ref(struct tegra20_i2s *i2s)
 {
        i2s->clk_refs++;
        if (i2s->clk_refs == 1)
                clk_enable(i2s->clk_i2s);
 }
 
-static void tegra_i2s_dec_clock_ref(struct tegra_i2s *i2s)
+static void tegra20_i2s_dec_clock_ref(struct tegra20_i2s *i2s)
 {
        BUG_ON(!i2s->clk_refs);
 
@@ -74,79 +74,79 @@ static void tegra_i2s_dec_clock_ref(struct tegra_i2s *i2s)
 }
 
 #ifdef CONFIG_DEBUG_FS
-static int tegra_i2s_show(struct seq_file *s, void *unused)
+static int tegra20_i2s_show(struct seq_file *s, void *unused)
 {
 #define REG(r) { r, #r }
        static const struct {
                int offset;
                const char *name;
        } regs[] = {
-               REG(TEGRA_I2S_CTRL),
-               REG(TEGRA_I2S_STATUS),
-               REG(TEGRA_I2S_TIMING),
-               REG(TEGRA_I2S_FIFO_SCR),
-               REG(TEGRA_I2S_PCM_CTRL),
-               REG(TEGRA_I2S_NW_CTRL),
-               REG(TEGRA_I2S_TDM_CTRL),
-               REG(TEGRA_I2S_TDM_TX_RX_CTRL),
+               REG(TEGRA20_I2S_CTRL),
+               REG(TEGRA20_I2S_STATUS),
+               REG(TEGRA20_I2S_TIMING),
+               REG(TEGRA20_I2S_FIFO_SCR),
+               REG(TEGRA20_I2S_PCM_CTRL),
+               REG(TEGRA20_I2S_NW_CTRL),
+               REG(TEGRA20_I2S_TDM_CTRL),
+               REG(TEGRA20_I2S_TDM_TX_RX_CTRL),
        };
 #undef REG
 
-       struct tegra_i2s *i2s = s->private;
+       struct tegra20_i2s *i2s = s->private;
        int i;
 
-       tegra_i2s_inc_clock_ref(i2s);
+       tegra20_i2s_inc_clock_ref(i2s);
 
        for (i = 0; i < ARRAY_SIZE(regs); i++) {
-               u32 val = tegra_i2s_read(i2s, regs[i].offset);
+               u32 val = tegra20_i2s_read(i2s, regs[i].offset);
                seq_printf(s, "%s = %08x\n", regs[i].name, val);
        }
 
-       tegra_i2s_dec_clock_ref(i2s);
+       tegra20_i2s_dec_clock_ref(i2s);
 
        return 0;
 }
 
-static int tegra_i2s_debug_open(struct inode *inode, struct file *file)
+static int tegra20_i2s_debug_open(struct inode *inode, struct file *file)
 {
-       return single_open(file, tegra_i2s_show, inode->i_private);
+       return single_open(file, tegra20_i2s_show, inode->i_private);
 }
 
-static const struct file_operations tegra_i2s_debug_fops = {
-       .open    = tegra_i2s_debug_open,
+static const struct file_operations tegra20_i2s_debug_fops = {
+       .open    = tegra20_i2s_debug_open,
        .read    = seq_read,
        .llseek  = seq_lseek,
        .release = single_release,
 };
 
-static void tegra_i2s_debug_add(struct tegra_i2s *i2s, int id)
+static void tegra20_i2s_debug_add(struct tegra20_i2s *i2s, int id)
 {
        char name[] = DRV_NAME ".0";
 
        snprintf(name, sizeof(name), DRV_NAME".%1d", id);
        i2s->debug = debugfs_create_file(name, S_IRUGO, snd_soc_debugfs_root,
-                                               i2s, &tegra_i2s_debug_fops);
+                                               i2s, &tegra20_i2s_debug_fops);
 }
 
-static void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
+static void tegra20_i2s_debug_remove(struct tegra20_i2s *i2s)
 {
        if (i2s->debug)
                debugfs_remove(i2s->debug);
 }
 #else
-static inline void tegra_i2s_debug_add(struct tegra_i2s *i2s, int id)
+static inline void tegra20_i2s_debug_add(struct tegra20_i2s *i2s, int id)
 {
 }
 
-static inline void tegra_i2s_debug_remove(struct tegra_i2s *i2s)
+static inline void tegra20_i2s_debug_remove(struct tegra20_i2s *i2s)
 {
 }
 #endif
 
-static int tegra_i2s_set_fmt(struct snd_soc_dai *dai,
+static int tegra20_i2s_set_fmt(struct snd_soc_dai *dai,
                                unsigned int fmt)
 {
-       struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
+       struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 
        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
        case SND_SOC_DAIFMT_NB_NF:
@@ -155,10 +155,10 @@ static int tegra_i2s_set_fmt(struct snd_soc_dai *dai,
                return -EINVAL;
        }
 
-       i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_MASTER_ENABLE;
+       i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_MASTER_ENABLE;
        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
        case SND_SOC_DAIFMT_CBS_CFS:
-               i2s->reg_ctrl |= TEGRA_I2S_CTRL_MASTER_ENABLE;
+               i2s->reg_ctrl |= TEGRA20_I2S_CTRL_MASTER_ENABLE;
                break;
        case SND_SOC_DAIFMT_CBM_CFM:
                break;
@@ -166,28 +166,28 @@ static int tegra_i2s_set_fmt(struct snd_soc_dai *dai,
                return -EINVAL;
        }
 
-       i2s->reg_ctrl &= ~(TEGRA_I2S_CTRL_BIT_FORMAT_MASK | 
-                               TEGRA_I2S_CTRL_LRCK_MASK);
+       i2s->reg_ctrl &= ~(TEGRA20_I2S_CTRL_BIT_FORMAT_MASK | 
+                               TEGRA20_I2S_CTRL_LRCK_MASK);
        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
        case SND_SOC_DAIFMT_DSP_A:
-               i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
-               i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
+               i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
+               i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
                break;
        case SND_SOC_DAIFMT_DSP_B:
-               i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_DSP;
-               i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_R_LOW;
+               i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_DSP;
+               i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_R_LOW;
                break;
        case SND_SOC_DAIFMT_I2S:
-               i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_I2S;
-               i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
+               i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_I2S;
+               i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
                break;
        case SND_SOC_DAIFMT_RIGHT_J:
-               i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_RJM;
-               i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
+               i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_RJM;
+               i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
                break;
        case SND_SOC_DAIFMT_LEFT_J:
-               i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_FORMAT_LJM;
-               i2s->reg_ctrl |= TEGRA_I2S_CTRL_LRCK_L_LOW;
+               i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_FORMAT_LJM;
+               i2s->reg_ctrl |= TEGRA20_I2S_CTRL_LRCK_L_LOW;
                break;
        default:
                return -EINVAL;
@@ -196,27 +196,27 @@ static int tegra_i2s_set_fmt(struct snd_soc_dai *dai,
        return 0;
 }
 
-static int tegra_i2s_hw_params(struct snd_pcm_substream *substream,
+static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream,
                                struct snd_pcm_hw_params *params,
                                struct snd_soc_dai *dai)
 {
         struct device *dev = substream->pcm->card->dev;
-       struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
+       struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
        u32 reg;
        int ret, sample_size, srate, i2sclock, bitcnt;
 
-       i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_BIT_SIZE_MASK;
+       i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_BIT_SIZE_MASK;
        switch (params_format(params)) {
        case SNDRV_PCM_FORMAT_S16_LE:
-               i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_16;
+               i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_16;
                sample_size = 16;
                break;
        case SNDRV_PCM_FORMAT_S24_LE:
-               i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_24;
+               i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_24;
                sample_size = 24;
                break;
        case SNDRV_PCM_FORMAT_S32_LE:
-               i2s->reg_ctrl |= TEGRA_I2S_CTRL_BIT_SIZE_32;
+               i2s->reg_ctrl |= TEGRA20_I2S_CTRL_BIT_SIZE_32;
                sample_size = 32;
                break;
        default:
@@ -235,73 +235,73 @@ static int tegra_i2s_hw_params(struct snd_pcm_substream *substream,
        }
 
        bitcnt = (i2sclock / (2 * srate)) - 1;
-       if (bitcnt < 0 || bitcnt > TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
+       if (bitcnt < 0 || bitcnt > TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
                return -EINVAL;
-       reg = bitcnt << TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
+       reg = bitcnt << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
 
        if (i2sclock % (2 * srate))
-               reg |= TEGRA_I2S_TIMING_NON_SYM_ENABLE;
+               reg |= TEGRA20_I2S_TIMING_NON_SYM_ENABLE;
 
-       tegra_i2s_inc_clock_ref(i2s);
+       tegra20_i2s_inc_clock_ref(i2s);
 
-       tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg);
+       tegra20_i2s_write(i2s, TEGRA20_I2S_TIMING, reg);
 
-       tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR,
-               TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
-               TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
+       tegra20_i2s_write(i2s, TEGRA20_I2S_FIFO_SCR,
+               TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
+               TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
 
-       tegra_i2s_dec_clock_ref(i2s);
+       tegra20_i2s_dec_clock_ref(i2s);
 
        return 0;
 }
 
-static void tegra_i2s_start_playback(struct tegra_i2s *i2s)
+static void tegra20_i2s_start_playback(struct tegra20_i2s *i2s)
 {
-       i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO1_ENABLE;
-       tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
+       i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO1_ENABLE;
+       tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
 }
 
-static void tegra_i2s_stop_playback(struct tegra_i2s *i2s)
+static void tegra20_i2s_stop_playback(struct tegra20_i2s *i2s)
 {
-       i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO1_ENABLE;
-       tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
+       i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO1_ENABLE;
+       tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
 }
 
-static void tegra_i2s_start_capture(struct tegra_i2s *i2s)
+static void tegra20_i2s_start_capture(struct tegra20_i2s *i2s)
 {
-       i2s->reg_ctrl |= TEGRA_I2S_CTRL_FIFO2_ENABLE;
-       tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
+       i2s->reg_ctrl |= TEGRA20_I2S_CTRL_FIFO2_ENABLE;
+       tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
 }
 
-static void tegra_i2s_stop_capture(struct tegra_i2s *i2s)
+static void tegra20_i2s_stop_capture(struct tegra20_i2s *i2s)
 {
-       i2s->reg_ctrl &= ~TEGRA_I2S_CTRL_FIFO2_ENABLE;
-       tegra_i2s_write(i2s, TEGRA_I2S_CTRL, i2s->reg_ctrl);
+       i2s->reg_ctrl &= ~TEGRA20_I2S_CTRL_FIFO2_ENABLE;
+       tegra20_i2s_write(i2s, TEGRA20_I2S_CTRL, i2s->reg_ctrl);
 }
 
-static int tegra_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
+static int tegra20_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
                                struct snd_soc_dai *dai)
 {
-       struct tegra_i2s *i2s = snd_soc_dai_get_drvdata(dai);
+       struct tegra20_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 
        switch (cmd) {
        case SNDRV_PCM_TRIGGER_START:
        case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
        case SNDRV_PCM_TRIGGER_RESUME:
-               tegra_i2s_inc_clock_ref(i2s);
+               tegra20_i2s_inc_clock_ref(i2s);
                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-                       tegra_i2s_start_playback(i2s);
+                       tegra20_i2s_start_playback(i2s);
                else
-                       tegra_i2s_start_capture(i2s);
+                       tegra20_i2s_start_capture(i2s);
                break;
        case SNDRV_PCM_TRIGGER_STOP:
        case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
        case SNDRV_PCM_TRIGGER_SUSPEND:
                if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-                       tegra_i2s_stop_playback(i2s);
+                       tegra20_i2s_stop_playback(i2s);
                else
-                       tegra_i2s_stop_capture(i2s);
-               tegra_i2s_dec_clock_ref(i2s);
+                       tegra20_i2s_stop_capture(i2s);
+               tegra20_i2s_dec_clock_ref(i2s);
                break;
        default:
                return -EINVAL;
@@ -310,9 +310,9 @@ static int tegra_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
        return 0;
 }
 
-static int tegra_i2s_probe(struct snd_soc_dai *dai)
+static int tegra20_i2s_probe(struct snd_soc_dai *dai)
 {
-       struct tegra_i2s * i2s = snd_soc_dai_get_drvdata(dai);
+       struct tegra20_i2s * i2s = snd_soc_dai_get_drvdata(dai);
 
        dai->capture_dma_data = &i2s->capture_dma_data;
        dai->playback_dma_data = &i2s->playback_dma_data;
@@ -320,16 +320,16 @@ static int tegra_i2s_probe(struct snd_soc_dai *dai)
        return 0;
 }
 
-static struct snd_soc_dai_ops tegra_i2s_dai_ops = {
-       .set_fmt        = tegra_i2s_set_fmt,
-       .hw_params      = tegra_i2s_hw_params,
-       .trigger        = tegra_i2s_trigger,
+static struct snd_soc_dai_ops tegra20_i2s_dai_ops = {
+       .set_fmt        = tegra20_i2s_set_fmt,
+       .hw_params      = tegra20_i2s_hw_params,
+       .trigger        = tegra20_i2s_trigger,
 };
 
-struct snd_soc_dai_driver tegra_i2s_dai[] = {
+struct snd_soc_dai_driver tegra20_i2s_dai[] = {
        {
                .name = DRV_NAME ".0",
-               .probe = tegra_i2s_probe,
+               .probe = tegra20_i2s_probe,
                .playback = {
                        .channels_min = 2,
                        .channels_max = 2,
@@ -342,12 +342,12 @@ struct snd_soc_dai_driver tegra_i2s_dai[] = {
                        .rates = SNDRV_PCM_RATE_8000_96000,
                        .formats = SNDRV_PCM_FMTBIT_S16_LE,
                },
-               .ops = &tegra_i2s_dai_ops,
+               .ops = &tegra20_i2s_dai_ops,
                .symmetric_rates = 1,
        },
        {
                .name = DRV_NAME ".1",
-               .probe = tegra_i2s_probe,
+               .probe = tegra20_i2s_probe,
                .playback = {
                        .channels_min = 2,
                        .channels_max = 2,
@@ -360,19 +360,19 @@ struct snd_soc_dai_driver tegra_i2s_dai[] = {
                        .rates = SNDRV_PCM_RATE_8000_96000,
                        .formats = SNDRV_PCM_FMTBIT_S16_LE,
                },
-               .ops = &tegra_i2s_dai_ops,
+               .ops = &tegra20_i2s_dai_ops,
                .symmetric_rates = 1,
        },
 };
 
-static __devinit int tegra_i2s_platform_probe(struct platform_device *pdev)
+static __devinit int tegra20_i2s_platform_probe(struct platform_device *pdev)
 {
-       struct tegra_i2s * i2s;
+       struct tegra20_i2s * i2s;
        struct resource *mem, *memregion, *dmareq;
        int ret;
 
        if ((pdev->id < 0) ||
-               (pdev->id >= ARRAY_SIZE(tegra_i2s_dai))) {
+               (pdev->id >= ARRAY_SIZE(tegra20_i2s_dai))) {
                dev_err(&pdev->dev, "ID %d out of range\n", pdev->id);
                return -EINVAL;
        }
@@ -381,22 +381,22 @@ static __devinit int tegra_i2s_platform_probe(struct platform_device *pdev)
         * FIXME: Until a codec driver exists for the tegra DAS, hard-code a
         * 1:1 mapping between audio controllers and audio ports.
         */
-       ret = tegra_das_connect_dap_to_dac(TEGRA_DAS_DAP_ID_1 + pdev->id,
-                                       TEGRA_DAS_DAP_SEL_DAC1 + pdev->id);
+       ret = tegra20_das_connect_dap_to_dac(TEGRA20_DAS_DAP_ID_1 + pdev->id,
+                                       TEGRA20_DAS_DAP_SEL_DAC1 + pdev->id);
        if (ret) {
                dev_err(&pdev->dev, "Can't set up DAP connection\n");
                return ret;
        }
-       ret = tegra_das_connect_dac_to_dap(TEGRA_DAS_DAC_ID_1 + pdev->id,
-                                       TEGRA_DAS_DAC_SEL_DAP1 + pdev->id);
+       ret = tegra20_das_connect_dac_to_dap(TEGRA20_DAS_DAC_ID_1 + pdev->id,
+                                       TEGRA20_DAS_DAC_SEL_DAP1 + pdev->id);
        if (ret) {
                dev_err(&pdev->dev, "Can't set up DAC connection\n");
                return ret;
        }
 
-       i2s = kzalloc(sizeof(struct tegra_i2s), GFP_KERNEL);
+       i2s = kzalloc(sizeof(struct tegra20_i2s), GFP_KERNEL);
        if (!i2s) {
-               dev_err(&pdev->dev, "Can't allocate tegra_i2s\n");
+               dev_err(&pdev->dev, "Can't allocate tegra20_i2s\n");
                ret = -ENOMEM;
                goto exit;
        }
@@ -438,26 +438,26 @@ static __devinit int tegra_i2s_platform_probe(struct platform_device *pdev)
                goto err_release;
        }
 
-       i2s->capture_dma_data.addr = mem->start + TEGRA_I2S_FIFO2;
+       i2s->capture_dma_data.addr = mem->start + TEGRA20_I2S_FIFO2;
        i2s->capture_dma_data.wrap = 4;
        i2s->capture_dma_data.width = 32;
        i2s->capture_dma_data.req_sel = dmareq->start;
 
-       i2s->playback_dma_data.addr = mem->start + TEGRA_I2S_FIFO1;
+       i2s->playback_dma_data.addr = mem->start + TEGRA20_I2S_FIFO1;
        i2s->playback_dma_data.wrap = 4;
        i2s->playback_dma_data.width = 32;
        i2s->playback_dma_data.req_sel = dmareq->start;
 
-       i2s->reg_ctrl = TEGRA_I2S_CTRL_FIFO_FORMAT_PACKED;
+       i2s->reg_ctrl = TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED;
 
-       ret = snd_soc_register_dai(&pdev->dev, &tegra_i2s_dai[pdev->id]);
+       ret = snd_soc_register_dai(&pdev->dev, &tegra20_i2s_dai[pdev->id]);
        if (ret) {
                dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
                ret = -ENOMEM;
                goto err_unmap;
        }
 
-       tegra_i2s_debug_add(i2s, pdev->id);
+       tegra20_i2s_debug_add(i2s, pdev->id);
 
        return 0;
 
@@ -473,14 +473,14 @@ exit:
        return ret;
 }
 
-static int __devexit tegra_i2s_platform_remove(struct platform_device *pdev)
+static int __devexit tegra20_i2s_platform_remove(struct platform_device *pdev)
 {
-       struct tegra_i2s *i2s = dev_get_drvdata(&pdev->dev);
+       struct tegra20_i2s *i2s = dev_get_drvdata(&pdev->dev);
        struct resource *res;
 
        snd_soc_unregister_dai(&pdev->dev);
 
-       tegra_i2s_debug_remove(i2s);
+       tegra20_i2s_debug_remove(i2s);
 
        iounmap(i2s->regs);
 
@@ -494,26 +494,26 @@ static int __devexit tegra_i2s_platform_remove(struct platform_device *pdev)
        return 0;
 }
 
-static struct platform_driver tegra_i2s_driver = {
+static struct platform_driver tegra20_i2s_driver = {
        .driver = {
                .name = DRV_NAME,
                .owner = THIS_MODULE,
        },
-       .probe = tegra_i2s_platform_probe,
-       .remove = __devexit_p(tegra_i2s_platform_remove),
+       .probe = tegra20_i2s_platform_probe,
+       .remove = __devexit_p(tegra20_i2s_platform_remove),
 };
 
-static int __init snd_tegra_i2s_init(void)
+static int __init snd_tegra20_i2s_init(void)
 {
-       return platform_driver_register(&tegra_i2s_driver);
+       return platform_driver_register(&tegra20_i2s_driver);
 }
-module_init(snd_tegra_i2s_init);
+module_init(snd_tegra20_i2s_init);
 
-static void __exit snd_tegra_i2s_exit(void)
+static void __exit snd_tegra20_i2s_exit(void)
 {
-       platform_driver_unregister(&tegra_i2s_driver);
+       platform_driver_unregister(&tegra20_i2s_driver);
 }
-module_exit(snd_tegra_i2s_exit);
+module_exit(snd_tegra20_i2s_exit);
 
 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
 MODULE_DESCRIPTION("Tegra I2S ASoC driver");
index 623450c..08fcb4b 100644 (file)
  *
  */
 
-#ifndef __TEGRA_I2S_H__
-#define __TEGRA_I2S_H__
+#ifndef __TEGRA20_I2S_H__
+#define __TEGRA20_I2S_H__
 
 #include "tegra_pcm.h"
 
-/* Register offsets from TEGRA_I2S1_BASE and TEGRA_I2S2_BASE */
-
-#define TEGRA_I2S_CTRL                                 0x00
-#define TEGRA_I2S_STATUS                               0x04
-#define TEGRA_I2S_TIMING                               0x08
-#define TEGRA_I2S_FIFO_SCR                             0x0c
-#define TEGRA_I2S_PCM_CTRL                             0x10
-#define TEGRA_I2S_NW_CTRL                              0x14
-#define TEGRA_I2S_TDM_CTRL                             0x20
-#define TEGRA_I2S_TDM_TX_RX_CTRL                       0x24
-#define TEGRA_I2S_FIFO1                                        0x40
-#define TEGRA_I2S_FIFO2                                        0x80
-
-/* Fields in TEGRA_I2S_CTRL */
-
-#define TEGRA_I2S_CTRL_FIFO2_TX_ENABLE                 (1 << 30)
-#define TEGRA_I2S_CTRL_FIFO1_ENABLE                    (1 << 29)
-#define TEGRA_I2S_CTRL_FIFO2_ENABLE                    (1 << 28)
-#define TEGRA_I2S_CTRL_FIFO1_RX_ENABLE                 (1 << 27)
-#define TEGRA_I2S_CTRL_FIFO_LPBK_ENABLE                        (1 << 26)
-#define TEGRA_I2S_CTRL_MASTER_ENABLE                   (1 << 25)
-
-#define TEGRA_I2S_LRCK_LEFT_LOW                                0
-#define TEGRA_I2S_LRCK_RIGHT_LOW                       1
-
-#define TEGRA_I2S_CTRL_LRCK_SHIFT                      24
-#define TEGRA_I2S_CTRL_LRCK_MASK                       (1                        << TEGRA_I2S_CTRL_LRCK_SHIFT)
-#define TEGRA_I2S_CTRL_LRCK_L_LOW                      (TEGRA_I2S_LRCK_LEFT_LOW  << TEGRA_I2S_CTRL_LRCK_SHIFT)
-#define TEGRA_I2S_CTRL_LRCK_R_LOW                      (TEGRA_I2S_LRCK_RIGHT_LOW << TEGRA_I2S_CTRL_LRCK_SHIFT)
-
-#define TEGRA_I2S_BIT_FORMAT_I2S                       0
-#define TEGRA_I2S_BIT_FORMAT_RJM                       1
-#define TEGRA_I2S_BIT_FORMAT_LJM                       2
-#define TEGRA_I2S_BIT_FORMAT_DSP                       3
-
-#define TEGRA_I2S_CTRL_BIT_FORMAT_SHIFT                        10
-#define TEGRA_I2S_CTRL_BIT_FORMAT_MASK                 (3                        << TEGRA_I2S_CTRL_BIT_FORMAT_SHIFT)
-#define TEGRA_I2S_CTRL_BIT_FORMAT_I2S                  (TEGRA_I2S_BIT_FORMAT_I2S << TEGRA_I2S_CTRL_BIT_FORMAT_SHIFT)
-#define TEGRA_I2S_CTRL_BIT_FORMAT_RJM                  (TEGRA_I2S_BIT_FORMAT_RJM << TEGRA_I2S_CTRL_BIT_FORMAT_SHIFT)
-#define TEGRA_I2S_CTRL_BIT_FORMAT_LJM                  (TEGRA_I2S_BIT_FORMAT_LJM << TEGRA_I2S_CTRL_BIT_FORMAT_SHIFT)
-#define TEGRA_I2S_CTRL_BIT_FORMAT_DSP                  (TEGRA_I2S_BIT_FORMAT_DSP << TEGRA_I2S_CTRL_BIT_FORMAT_SHIFT)
-
-#define TEGRA_I2S_BIT_SIZE_16                          0
-#define TEGRA_I2S_BIT_SIZE_20                          1
-#define TEGRA_I2S_BIT_SIZE_24                          2
-#define TEGRA_I2S_BIT_SIZE_32                          3
-
-#define TEGRA_I2S_CTRL_BIT_SIZE_SHIFT                  8
-#define TEGRA_I2S_CTRL_BIT_SIZE_MASK                   (3                     << TEGRA_I2S_CTRL_BIT_SIZE_SHIFT)
-#define TEGRA_I2S_CTRL_BIT_SIZE_16                     (TEGRA_I2S_BIT_SIZE_16 << TEGRA_I2S_CTRL_BIT_SIZE_SHIFT)
-#define TEGRA_I2S_CTRL_BIT_SIZE_20                     (TEGRA_I2S_BIT_SIZE_20 << TEGRA_I2S_CTRL_BIT_SIZE_SHIFT)
-#define TEGRA_I2S_CTRL_BIT_SIZE_24                     (TEGRA_I2S_BIT_SIZE_24 << TEGRA_I2S_CTRL_BIT_SIZE_SHIFT)
-#define TEGRA_I2S_CTRL_BIT_SIZE_32                     (TEGRA_I2S_BIT_SIZE_32 << TEGRA_I2S_CTRL_BIT_SIZE_SHIFT)
-
-#define TEGRA_I2S_FIFO_16_LSB                          0
-#define TEGRA_I2S_FIFO_20_LSB                          1
-#define TEGRA_I2S_FIFO_24_LSB                          2
-#define TEGRA_I2S_FIFO_32                              3
-#define TEGRA_I2S_FIFO_PACKED                          7
-
-#define TEGRA_I2S_CTRL_FIFO_FORMAT_SHIFT               4
-#define TEGRA_I2S_CTRL_FIFO_FORMAT_MASK                        (7                     << TEGRA_I2S_CTRL_FIFO_FORMAT_SHIFT)
-#define TEGRA_I2S_CTRL_FIFO_FORMAT_16_LSB              (TEGRA_I2S_FIFO_16_LSB << TEGRA_I2S_CTRL_FIFO_FORMAT_SHIFT)
-#define TEGRA_I2S_CTRL_FIFO_FORMAT_20_LSB              (TEGRA_I2S_FIFO_20_LSB << TEGRA_I2S_CTRL_FIFO_FORMAT_SHIFT)
-#define TEGRA_I2S_CTRL_FIFO_FORMAT_24_LSB              (TEGRA_I2S_FIFO_24_LSB << TEGRA_I2S_CTRL_FIFO_FORMAT_SHIFT)
-#define TEGRA_I2S_CTRL_FIFO_FORMAT_32                  (TEGRA_I2S_FIFO_32     << TEGRA_I2S_CTRL_FIFO_FORMAT_SHIFT)
-#define TEGRA_I2S_CTRL_FIFO_FORMAT_PACKED              (TEGRA_I2S_FIFO_PACKED << TEGRA_I2S_CTRL_FIFO_FORMAT_SHIFT)
-
-#define TEGRA_I2S_CTRL_IE_FIFO1_ERR                    (1 << 3)
-#define TEGRA_I2S_CTRL_IE_FIFO2_ERR                    (1 << 2)
-#define TEGRA_I2S_CTRL_QE_FIFO1                                (1 << 1)
-#define TEGRA_I2S_CTRL_QE_FIFO2                                (1 << 0)
-
-/* Fields in TEGRA_I2S_STATUS */
-
-#define TEGRA_I2S_STATUS_FIFO1_RDY                     (1 << 31)
-#define TEGRA_I2S_STATUS_FIFO2_RDY                     (1 << 30)
-#define TEGRA_I2S_STATUS_FIFO1_BSY                     (1 << 29)
-#define TEGRA_I2S_STATUS_FIFO2_BSY                     (1 << 28)
-#define TEGRA_I2S_STATUS_FIFO1_ERR                     (1 << 3)
-#define TEGRA_I2S_STATUS_FIFO2_ERR                     (1 << 2)
-#define TEGRA_I2S_STATUS_QS_FIFO1                      (1 << 1)
-#define TEGRA_I2S_STATUS_QS_FIFO2                      (1 << 0)
-
-/* Fields in TEGRA_I2S_TIMING */
-
-#define TEGRA_I2S_TIMING_NON_SYM_ENABLE                        (1 << 12)
-#define TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT       0
-#define TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US     0x7fff
-#define TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK                (TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << TEGRA_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT)
-
-/* Fields in TEGRA_I2S_FIFO_SCR */
-
-#define TEGRA_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT        24
-#define TEGRA_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT        16
-#define TEGRA_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK  0x3f
-
-#define TEGRA_I2S_FIFO_SCR_FIFO2_CLR                   (1 << 12)
-#define TEGRA_I2S_FIFO_SCR_FIFO1_CLR                   (1 << 8)
-
-#define TEGRA_I2S_FIFO_ATN_LVL_ONE_SLOT                        0
-#define TEGRA_I2S_FIFO_ATN_LVL_FOUR_SLOTS              1
-#define TEGRA_I2S_FIFO_ATN_LVL_EIGHT_SLOTS             2
-#define TEGRA_I2S_FIFO_ATN_LVL_TWELVE_SLOTS            3
-
-#define TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT         4
-#define TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK          (3 << TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
-#define TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT      (TEGRA_I2S_FIFO_ATN_LVL_ONE_SLOT     << TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
-#define TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS    (TEGRA_I2S_FIFO_ATN_LVL_FOUR_SLOTS   << TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
-#define TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS   (TEGRA_I2S_FIFO_ATN_LVL_EIGHT_SLOTS  << TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
-#define TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS  (TEGRA_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
-
-#define TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT         0
-#define TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK          (3 << TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
-#define TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT      (TEGRA_I2S_FIFO_ATN_LVL_ONE_SLOT     << TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
-#define TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS    (TEGRA_I2S_FIFO_ATN_LVL_FOUR_SLOTS   << TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
-#define TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS   (TEGRA_I2S_FIFO_ATN_LVL_EIGHT_SLOTS  << TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
-#define TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS  (TEGRA_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
-
-struct tegra_i2s {
+/* Register offsets from TEGRA20_I2S1_BASE and TEGRA20_I2S2_BASE */
+
+#define TEGRA20_I2S_CTRL                               0x00
+#define TEGRA20_I2S_STATUS                             0x04
+#define TEGRA20_I2S_TIMING                             0x08
+#define TEGRA20_I2S_FIFO_SCR                           0x0c
+#define TEGRA20_I2S_PCM_CTRL                           0x10
+#define TEGRA20_I2S_NW_CTRL                            0x14
+#define TEGRA20_I2S_TDM_CTRL                           0x20
+#define TEGRA20_I2S_TDM_TX_RX_CTRL                     0x24
+#define TEGRA20_I2S_FIFO1                              0x40
+#define TEGRA20_I2S_FIFO2                              0x80
+
+/* Fields in TEGRA20_I2S_CTRL */
+
+#define TEGRA20_I2S_CTRL_FIFO2_TX_ENABLE               (1 << 30)
+#define TEGRA20_I2S_CTRL_FIFO1_ENABLE                  (1 << 29)
+#define TEGRA20_I2S_CTRL_FIFO2_ENABLE                  (1 << 28)
+#define TEGRA20_I2S_CTRL_FIFO1_RX_ENABLE               (1 << 27)
+#define TEGRA20_I2S_CTRL_FIFO_LPBK_ENABLE              (1 << 26)
+#define TEGRA20_I2S_CTRL_MASTER_ENABLE                 (1 << 25)
+
+#define TEGRA20_I2S_LRCK_LEFT_LOW                      0
+#define TEGRA20_I2S_LRCK_RIGHT_LOW                     1
+
+#define TEGRA20_I2S_CTRL_LRCK_SHIFT                    24
+#define TEGRA20_I2S_CTRL_LRCK_MASK                     (1                          << TEGRA20_I2S_CTRL_LRCK_SHIFT)
+#define TEGRA20_I2S_CTRL_LRCK_L_LOW                    (TEGRA20_I2S_LRCK_LEFT_LOW  << TEGRA20_I2S_CTRL_LRCK_SHIFT)
+#define TEGRA20_I2S_CTRL_LRCK_R_LOW                    (TEGRA20_I2S_LRCK_RIGHT_LOW << TEGRA20_I2S_CTRL_LRCK_SHIFT)
+
+#define TEGRA20_I2S_BIT_FORMAT_I2S                     0
+#define TEGRA20_I2S_BIT_FORMAT_RJM                     1
+#define TEGRA20_I2S_BIT_FORMAT_LJM                     2
+#define TEGRA20_I2S_BIT_FORMAT_DSP                     3
+
+#define TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT              10
+#define TEGRA20_I2S_CTRL_BIT_FORMAT_MASK               (3                          << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
+#define TEGRA20_I2S_CTRL_BIT_FORMAT_I2S                        (TEGRA20_I2S_BIT_FORMAT_I2S << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
+#define TEGRA20_I2S_CTRL_BIT_FORMAT_RJM                        (TEGRA20_I2S_BIT_FORMAT_RJM << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
+#define TEGRA20_I2S_CTRL_BIT_FORMAT_LJM                        (TEGRA20_I2S_BIT_FORMAT_LJM << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
+#define TEGRA20_I2S_CTRL_BIT_FORMAT_DSP                        (TEGRA20_I2S_BIT_FORMAT_DSP << TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT)
+
+#define TEGRA20_I2S_BIT_SIZE_16                                0
+#define TEGRA20_I2S_BIT_SIZE_20                                1
+#define TEGRA20_I2S_BIT_SIZE_24                                2
+#define TEGRA20_I2S_BIT_SIZE_32                                3
+
+#define TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT                        8
+#define TEGRA20_I2S_CTRL_BIT_SIZE_MASK                 (3                       << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
+#define TEGRA20_I2S_CTRL_BIT_SIZE_16                   (TEGRA20_I2S_BIT_SIZE_16 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
+#define TEGRA20_I2S_CTRL_BIT_SIZE_20                   (TEGRA20_I2S_BIT_SIZE_20 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
+#define TEGRA20_I2S_CTRL_BIT_SIZE_24                   (TEGRA20_I2S_BIT_SIZE_24 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
+#define TEGRA20_I2S_CTRL_BIT_SIZE_32                   (TEGRA20_I2S_BIT_SIZE_32 << TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT)
+
+#define TEGRA20_I2S_FIFO_16_LSB                                0
+#define TEGRA20_I2S_FIFO_20_LSB                                1
+#define TEGRA20_I2S_FIFO_24_LSB                                2
+#define TEGRA20_I2S_FIFO_32                            3
+#define TEGRA20_I2S_FIFO_PACKED                                7
+
+#define TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT             4
+#define TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK              (7                       << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
+#define TEGRA20_I2S_CTRL_FIFO_FORMAT_16_LSB            (TEGRA20_I2S_FIFO_16_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
+#define TEGRA20_I2S_CTRL_FIFO_FORMAT_20_LSB            (TEGRA20_I2S_FIFO_20_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
+#define TEGRA20_I2S_CTRL_FIFO_FORMAT_24_LSB            (TEGRA20_I2S_FIFO_24_LSB << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
+#define TEGRA20_I2S_CTRL_FIFO_FORMAT_32                        (TEGRA20_I2S_FIFO_32     << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
+#define TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED            (TEGRA20_I2S_FIFO_PACKED << TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT)
+
+#define TEGRA20_I2S_CTRL_IE_FIFO1_ERR                  (1 << 3)
+#define TEGRA20_I2S_CTRL_IE_FIFO2_ERR                  (1 << 2)
+#define TEGRA20_I2S_CTRL_QE_FIFO1                      (1 << 1)
+#define TEGRA20_I2S_CTRL_QE_FIFO2                      (1 << 0)
+
+/* Fields in TEGRA20_I2S_STATUS */
+
+#define TEGRA20_I2S_STATUS_FIFO1_RDY                   (1 << 31)
+#define TEGRA20_I2S_STATUS_FIFO2_RDY                   (1 << 30)
+#define TEGRA20_I2S_STATUS_FIFO1_BSY                   (1 << 29)
+#define TEGRA20_I2S_STATUS_FIFO2_BSY                   (1 << 28)
+#define TEGRA20_I2S_STATUS_FIFO1_ERR                   (1 << 3)
+#define TEGRA20_I2S_STATUS_FIFO2_ERR                   (1 << 2)
+#define TEGRA20_I2S_STATUS_QS_FIFO1                    (1 << 1)
+#define TEGRA20_I2S_STATUS_QS_FIFO2                    (1 << 0)
+
+/* Fields in TEGRA20_I2S_TIMING */
+
+#define TEGRA20_I2S_TIMING_NON_SYM_ENABLE              (1 << 12)
+#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT     0
+#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US   0x7fff
+#define TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK      (TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT)
+
+/* Fields in TEGRA20_I2S_FIFO_SCR */
+
+#define TEGRA20_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT      24
+#define TEGRA20_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT      16
+#define TEGRA20_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK                0x3f
+
+#define TEGRA20_I2S_FIFO_SCR_FIFO2_CLR                 (1 << 12)
+#define TEGRA20_I2S_FIFO_SCR_FIFO1_CLR                 (1 << 8)
+
+#define TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT              0
+#define TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS            1
+#define TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS           2
+#define TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS          3
+
+#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT       4
+#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK                (3                                     << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
+#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT    (TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT     << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
+#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS  (TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS   << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
+#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS  << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
+#define TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS        (TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT)
+
+#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT       0
+#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK                (3                                     << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
+#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT    (TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT     << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
+#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS  (TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS   << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
+#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS (TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS  << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
+#define TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS        (TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS << TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT)
+
+struct tegra20_i2s {
        struct clk *clk_i2s;
        int clk_refs;
        struct tegra_pcm_dma_params capture_dma_data;
index 021716d..f2c1a10 100644 (file)
@@ -347,7 +347,7 @@ static struct snd_soc_dai_link tegra_wm8903_dai = {
        .stream_name = "WM8903 PCM",
        .codec_name = "wm8903.0-001a",
        .platform_name = "tegra-pcm-audio",
-       .cpu_dai_name = "tegra-i2s.0",
+       .cpu_dai_name = "tegra20-i2s.0",
        .codec_dai_name = "wm8903-hifi",
        .init = tegra_wm8903_init,
        .ops = &tegra_wm8903_ops,