amd64_edac: Fix DRAM base macros
Borislav Petkov [Mon, 21 Feb 2011 18:33:10 +0000 (19:33 +0100)]
Return unsigned u8 values only.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>

drivers/edac/amd64_edac.c
drivers/edac/amd64_edac.h

index 8d9def5..e6adc73 100644 (file)
@@ -621,7 +621,6 @@ static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr)
        BUG_ON(node_id > 7);
 
        intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
-
        if (intlv_shift == 0) {
                debugf1("    InputAddr 0x%lx translates to DramAddr of "
                        "same value\n", (unsigned long)input_addr);
@@ -1192,7 +1191,7 @@ static void read_dram_ctl_register(struct amd64_pvt *pvt)
 static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
                                bool hi_range_sel, u8 intlv_en)
 {
-       u32 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1;
+       u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1;
 
        if (dct_ganging_enabled(pvt))
                return 0;
index 6220bae..11be36a 100644 (file)
 #define DRAM_BASE_LO                   0x40
 #define DRAM_LIMIT_LO                  0x44
 
-#define dram_intlv_en(pvt, i)          ((pvt->ranges[i].base.lo >> 8) & 0x7)
-#define dram_rw(pvt, i)                        (pvt->ranges[i].base.lo & 0x3)
-#define dram_intlv_sel(pvt, i)         ((pvt->ranges[i].lim.lo >> 8) & 0x7)
-#define dram_dst_node(pvt, i)          (pvt->ranges[i].lim.lo & 0x7)
+#define dram_intlv_en(pvt, i)          ((u8)((pvt->ranges[i].base.lo >> 8) & 0x7))
+#define dram_rw(pvt, i)                        ((u8)(pvt->ranges[i].base.lo & 0x3))
+#define dram_intlv_sel(pvt, i)         ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
+#define dram_dst_node(pvt, i)          ((u8)(pvt->ranges[i].lim.lo & 0x7))
 
 #define DHAR                           0xf0
 #define dhar_valid(pvt)                        ((pvt)->dhar & BIT(0))