Merge remote-tracking branch 'origin/dev/k3.3-rc1-iommu' into android-tegra-nv-3.1
Rohan Somvanshi [Wed, 1 Feb 2012 10:33:06 +0000 (15:33 +0530)]
Change-Id: I9001bb291779f107bbcb593d48f9f0f734074d0e

231 files changed:
Documentation/virtual/kvm/api.txt
Makefile
arch/arm/configs/tegra3_android_defconfig
arch/arm/configs/tegra3_defconfig
arch/arm/configs/tegra_cardhu_mods_ldk_defconfig [new file with mode: 0644]
arch/arm/configs/tegra_defconfig
arch/arm/configs/tegra_p1852_gnu_linux_defconfig [new file with mode: 0644]
arch/arm/include/asm/sizes.h
arch/arm/mach-tegra/Kconfig
arch/arm/mach-tegra/Makefile
arch/arm/mach-tegra/baseband-xmm-power.c
arch/arm/mach-tegra/baseband-xmm-power2.c
arch/arm/mach-tegra/board-cardhu-panel.c
arch/arm/mach-tegra/board-cardhu-sensors.c
arch/arm/mach-tegra/board-cardhu.c
arch/arm/mach-tegra/board-enterprise-panel.c
arch/arm/mach-tegra/board-enterprise-power.c
arch/arm/mach-tegra/board-enterprise.c
arch/arm/mach-tegra/board-harmony-power.c
arch/arm/mach-tegra/board-kai-kbc.c [new file with mode: 0644]
arch/arm/mach-tegra/board-kai-memory.c [new file with mode: 0644]
arch/arm/mach-tegra/board-kai-panel.c [new file with mode: 0644]
arch/arm/mach-tegra/board-kai-pinmux.c [new file with mode: 0644]
arch/arm/mach-tegra/board-kai-power.c [new file with mode: 0644]
arch/arm/mach-tegra/board-kai-sdhci.c [new file with mode: 0644]
arch/arm/mach-tegra/board-kai.c [new file with mode: 0644]
arch/arm/mach-tegra/board-kai.h [new file with mode: 0644]
arch/arm/mach-tegra/board-touch-kai-raydium_spi.c [new file with mode: 0644]
arch/arm/mach-tegra/board-touch-kai-synaptics-spi.c [new file with mode: 0644]
arch/arm/mach-tegra/board-ventana-panel.c
arch/arm/mach-tegra/board-ventana-sensors.c
arch/arm/mach-tegra/board-ventana.c
arch/arm/mach-tegra/board-whistler-panel.c
arch/arm/mach-tegra/board-whistler-pinmux.c
arch/arm/mach-tegra/board-whistler.c
arch/arm/mach-tegra/board.h
arch/arm/mach-tegra/clock.h
arch/arm/mach-tegra/common.c
arch/arm/mach-tegra/cpu-tegra.c
arch/arm/mach-tegra/devices.c
arch/arm/mach-tegra/devices.h
arch/arm/mach-tegra/include/mach/dc.h
arch/arm/mach-tegra/include/mach/uncompress.h
arch/arm/mach-tegra/latency_allowance.c
arch/arm/mach-tegra/pcie.c
arch/arm/mach-tegra/pm-t3.c
arch/arm/mach-tegra/pm.c
arch/arm/mach-tegra/tegra3_actmon.c
arch/arm/mach-tegra/tegra3_clocks.c
arch/arm/mach-tegra/tegra3_tsensor.c
arch/arm/mach-tegra/usb_phy.c
arch/arm/tools/mach-types
arch/x86/include/asm/amd_nb.h
arch/x86/kernel/amd_nb.c
arch/x86/kernel/kvmclock.c
arch/x86/kvm/i8254.c
arch/x86/mm/mmap.c
arch/x86/pci/Makefile
arch/x86/pci/acpi.c
arch/x86/pci/amd_bus.c
drivers/gpu/drm/radeon/r100.c
drivers/gpu/drm/radeon/r600_hdmi.c
drivers/gpu/drm/radeon/radeon_device.c
drivers/gpu/drm/radeon/rs600.c
drivers/gpu/ion/ion.c
drivers/gpu/ion/ion_iommu_heap.c
drivers/gpu/ion/ion_priv.h
drivers/gpu/ion/tegra/tegra_ion.c
drivers/hid/hid-core.c
drivers/hwmon/tegra-tsensor.c
drivers/i2c/busses/i2c-tegra.c
drivers/input/touchscreen/Kconfig
drivers/input/touchscreen/Makefile
drivers/input/touchscreen/rm31080a_ts.c [new file with mode: 0644]
drivers/input/touchscreen/rm31080a_ts.h [new file with mode: 0644]
drivers/input/touchscreen/rmi4/Makefile [new file with mode: 0644]
drivers/input/touchscreen/rmi4/rmi_bus.c [new file with mode: 0644]
drivers/input/touchscreen/rmi4/rmi_dev.c [new file with mode: 0644]
drivers/input/touchscreen/rmi4/rmi_driver.c [new file with mode: 0644]
drivers/input/touchscreen/rmi4/rmi_driver.h [new file with mode: 0644]
drivers/input/touchscreen/rmi4/rmi_f01.c [new file with mode: 0644]
drivers/input/touchscreen/rmi4/rmi_f09.c [new file with mode: 0644]
drivers/input/touchscreen/rmi4/rmi_f11.c [new file with mode: 0644]
drivers/input/touchscreen/rmi4/rmi_f19.c [new file with mode: 0644]
drivers/input/touchscreen/rmi4/rmi_f34.c [new file with mode: 0644]
drivers/input/touchscreen/rmi4/rmi_f54.c [new file with mode: 0644]
drivers/input/touchscreen/rmi4/rmi_i2c.c [new file with mode: 0644]
drivers/input/touchscreen/rmi4/rmi_spi.c [new file with mode: 0644]
drivers/iommu/Kconfig
drivers/iommu/Makefile
drivers/iommu/tegra-gart.c [new file with mode: 0644]
drivers/md/raid1.c
drivers/media/video/tegra/mediaserver/tegra_mediaserver.c
drivers/media/video/tegra/nvavp/nvavp_dev.c
drivers/media/video/tegra/ov2710.c
drivers/media/video/tegra/ov5650.c
drivers/media/video/tegra/sh532u.c
drivers/media/video/tegra/ssl3250a.c
drivers/media/video/tegra/tegra_camera.c
drivers/media/video/tegra/tps61050.c
drivers/mfd/tps65910-irq.c
drivers/mfd/tps65910.c
drivers/misc/ti-st/st_core.c
drivers/misc/ti-st/st_kim.c
drivers/misc/ti-st/st_ll.c
drivers/mmc/core/sd.c
drivers/mmc/host/sdhci-tegra.c
drivers/mmc/host/sdhci.c
drivers/mmc/host/sdhci.h
drivers/mtd/mtd_blkdevs.c
drivers/mtd/mtdoops.c
drivers/mtd/tests/mtd_stresstest.c
drivers/mtd/ubi/eba.c
drivers/mtd/ubi/ubi.h
drivers/mtd/ubi/wl.c
drivers/net/usb/raw_ip_net.c
drivers/net/wireless/rtlwifi/rtl8192se/fw.c
drivers/pci/msi.c
drivers/platform/x86/ideapad-laptop.c
drivers/pnp/quirks.c
drivers/regulator/Kconfig
drivers/regulator/Makefile
drivers/regulator/tps62360-regulator.c [new file with mode: 0644]
drivers/regulator/tps65910-regulator.c
drivers/rtc/interface.c
drivers/scsi/mpt2sas/mpt2sas_base.c
drivers/scsi/mpt2sas/mpt2sas_scsih.c
drivers/spi/spi-tegra.c
drivers/usb/class/cdc-acm.c
drivers/usb/host/ehci-hcd.c
drivers/usb/host/ehci-tegra.c
drivers/usb/host/ehci.h
drivers/usb/serial/baseband_usb_chr.c
drivers/video/tegra/dc/dc.c
drivers/video/tegra/dc/dc_priv.h
drivers/video/tegra/dc/dsi.c
drivers/video/tegra/dc/ext/dev.c
drivers/video/tegra/dc/nvsd.c
drivers/video/tegra/host/Makefile
drivers/video/tegra/host/bus.c
drivers/video/tegra/host/bus_client.c [new file with mode: 0644]
drivers/video/tegra/host/bus_client.h [new file with mode: 0644]
drivers/video/tegra/host/chip_support.h
drivers/video/tegra/host/dev.c
drivers/video/tegra/host/dev.h
drivers/video/tegra/host/gr3d/gr3d.c
drivers/video/tegra/host/gr3d/gr3d_t20.c
drivers/video/tegra/host/gr3d/gr3d_t30.c
drivers/video/tegra/host/gr3d/scale3d.c
drivers/video/tegra/host/host1x/Makefile
drivers/video/tegra/host/host1x/host1x_cdma.c
drivers/video/tegra/host/host1x/host1x_channel.c
drivers/video/tegra/host/host1x/host1x_cpuaccess.c [deleted file]
drivers/video/tegra/host/host1x/host1x_syncpt.c
drivers/video/tegra/host/mpe/mpe.c
drivers/video/tegra/host/nvhost_acm.c
drivers/video/tegra/host/nvhost_acm.h
drivers/video/tegra/host/nvhost_cdma.c
drivers/video/tegra/host/nvhost_cdma.h
drivers/video/tegra/host/nvhost_channel.c
drivers/video/tegra/host/nvhost_channel.h
drivers/video/tegra/host/nvhost_cpuaccess.c [deleted file]
drivers/video/tegra/host/nvhost_cpuaccess.h [deleted file]
drivers/video/tegra/host/nvhost_syncpt.c
drivers/video/tegra/host/nvhost_syncpt.h
drivers/video/tegra/host/t20/t20.c
drivers/video/tegra/host/t20/t20.h
drivers/video/tegra/host/t30/t30.c
drivers/watchdog/tegra_wdt.c
drivers/xen/xenbus/xenbus_xs.c
fs/ext4/super.c
fs/nfs/callback_proc.c
fs/nfs/file.c
fs/nfs/nfs4proc.c
fs/nfs/nfs4xdr.c
fs/nfs/super.c
include/linux/genalloc.h
include/linux/i2c-tegra.h
include/linux/memcontrol.h
include/linux/mfd/tps65910.h
include/linux/mmc/sdhci.h
include/linux/nfs_xdr.h
include/linux/nvhost.h
include/linux/nvhost_ioctl.h
include/linux/pci_regs.h
include/linux/platform_data/rm31080a_ts.h [new file with mode: 0644]
include/linux/regulator/tps62360.h [new file with mode: 0644]
include/linux/rmi.h [new file with mode: 0644]
include/linux/sunrpc/xdr.h
include/linux/tegra_audio.h
include/linux/ti_wilink_st.h
include/linux/usb/usbnet.h
include/linux/wl12xx.h
include/media/ov5650.h
include/xen/interface/io/xs_wire.h
init/do_mounts.c
kernel/sched.c
mm/filemap.c
mm/memcontrol.c
mm/slub.c
net/mac80211/wpa.c
net/sunrpc/xdr.c
security/integrity/ima/ima_api.c
security/integrity/ima/ima_queue.c
sound/pci/hda/hda_local.h
sound/pci/hda/hda_proc.c
sound/pci/hda/patch_cirrus.c
sound/pci/hda/patch_conexant.c
sound/pci/hda/patch_sigmatel.c
sound/pci/hda/patch_via.c
sound/pci/ice1712/amp.c
sound/soc/codecs/wm8753.c
sound/soc/codecs/wm8903.c
sound/soc/tegra/Kconfig
sound/soc/tegra/Makefile
sound/soc/tegra/tegra20_das.c
sound/soc/tegra/tegra20_das.h
sound/soc/tegra/tegra30_ahub.c
sound/soc/tegra/tegra30_dam.c
sound/soc/tegra/tegra30_i2s.c
sound/soc/tegra/tegra_aic326x.c
sound/soc/tegra/tegra_asoc_utils.c
sound/soc/tegra/tegra_asoc_utils.h
sound/soc/tegra/tegra_max98088.c
sound/soc/tegra/tegra_max98095.c [new file with mode: 0644]
sound/soc/tegra/tegra_pcm.c
sound/soc/tegra/tegra_pcm.h
sound/soc/tegra/tegra_wm8753.c
sound/soc/tegra/tegra_wm8903.c
sound/usb/usx2y/usb_stream.c
virt/kvm/assigned-dev.c

index b0e4b9c..13ab837 100644 (file)
@@ -1131,6 +1131,13 @@ following flags are specified:
 /* Depends on KVM_CAP_IOMMU */
 #define KVM_DEV_ASSIGN_ENABLE_IOMMU    (1 << 0)
 
+The KVM_DEV_ASSIGN_ENABLE_IOMMU flag is a mandatory option to ensure
+isolation of the device.  Usages not specifying this flag are deprecated.
+
+Only PCI header type 0 devices with PCI BAR resources are supported by
+device assignment.  The user requesting this ioctl must have read/write
+access to the PCI sysfs resource files associated with the device.
+
 4.49 KVM_DEASSIGN_PCI_DEVICE
 
 Capability: KVM_CAP_DEVICE_DEASSIGNMENT
index feeb6ce..64562ab 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,6 @@
 VERSION = 3
 PATCHLEVEL = 1
-SUBLEVEL = 9
+SUBLEVEL = 10
 EXTRAVERSION =
 NAME = "Divemaster Edition"
 
index 4332ea4..e77a095 100644 (file)
@@ -27,6 +27,7 @@ CONFIG_GPIO_PCA953X=y
 CONFIG_ARCH_TEGRA_3x_SOC=y
 CONFIG_MACH_CARDHU=y
 CONFIG_MACH_TEGRA_ENTERPRISE=y
+CONFIG_MACH_KAI=y
 CONFIG_TEGRA_PWM=y
 CONFIG_TEGRA_EMC_SCALING_ENABLE=y
 CONFIG_TEGRA_CLOCK_DEBUG_WRITE=y
@@ -239,6 +240,7 @@ CONFIG_INPUT_JOYSTICK=y
 CONFIG_JOYSTICK_XPAD=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ATMEL_MXT=y
+CONFIG_TOUCHSCREEN_RM31080A=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_UINPUT=y
 CONFIG_INPUT_GPIO=y
index 348cf79..fdbdfaf 100644 (file)
@@ -303,11 +303,12 @@ CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
 CONFIG_TEGRA_NVAVP=y
 CONFIG_VIDEO_OV5650=m
 CONFIG_VIDEO_OV2710=m
-CONFIG_TORCH_SSL3250A=y
-CONFIG_TORCH_TPS61050=y
-CONFIG_VIDEO_SH532U=y
+CONFIG_TORCH_SSL3250A=m
+CONFIG_TORCH_TPS61050=m
+CONFIG_VIDEO_SH532U=m
 CONFIG_USB_VIDEO_CLASS=y
 # CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_VGA_ARB is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=y
 CONFIG_FB=y
 CONFIG_TEGRA_GRHOST=y
diff --git a/arch/arm/configs/tegra_cardhu_mods_ldk_defconfig b/arch/arm/configs/tegra_cardhu_mods_ldk_defconfig
new file mode 100644 (file)
index 0000000..6672284
--- /dev/null
@@ -0,0 +1,297 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+# CONFIG_ELF_CORE is not set
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_TEGRA=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_ARCH_TEGRA_3x_SOC=y
+CONFIG_TEGRA_PCI=y
+CONFIG_MACH_CARDHU=y
+CONFIG_MACH_TEGRA_ENTERPRISE=y
+CONFIG_TEGRA_EMC_SCALING_ENABLE=y
+CONFIG_TEGRA_EMC_TO_DDR_CLOCK=2
+CONFIG_USB_HOTPLUG=y
+CONFIG_ARM_ERRATA_742230=y
+CONFIG_ARM_ERRATA_743622=y
+CONFIG_ARM_ERRATA_751472=y
+CONFIG_ARM_ERRATA_752520=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_HIGHMEM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=m
+CONFIG_NET_KEY=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_CUBIC=m
+# CONFIG_TCP_CONG_HTCP is not set
+CONFIG_TCP_CONG_VEGAS=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_ILLINOIS=m
+# CONFIG_IPV6 is not set
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+# CONFIG_NET_ACTIVITY_STATS is not set
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_MQPRIO=m
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_MISC_DEVICES=y
+CONFIG_AD525X_DPOT=y
+CONFIG_AD525X_DPOT_I2C=y
+CONFIG_ICS932S401=y
+CONFIG_APDS9802ALS=y
+CONFIG_SENSORS_NCT1008=y
+CONFIG_ISL29003=y
+CONFIG_SENSORS_AK8975=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+CONFIG_R8169=y
+# CONFIG_NETDEV_10000 is not set
+CONFIG_BCM4329=m
+CONFIG_BCM4329_FW_PATH="/lib/firmware/bcm4329/fw_bcm4329.bin"
+CONFIG_BCM4329_NVRAM_PATH="/lib/firmware/bcm4329/nvram.txt"
+CONFIG_BCM4329_WIFI_CONTROL_FUNC=y
+CONFIG_USB_CATC=y
+CONFIG_USB_KAWETH=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_RTL8150=y
+CONFIG_USB_USBNET=y
+# CONFIG_USB_NET_CDCETHER is not set
+# CONFIG_USB_NET_CDC_NCM is not set
+CONFIG_USB_NET_DM9601=y
+CONFIG_USB_NET_SMSC75XX=y
+CONFIG_USB_NET_SMSC95XX=y
+# CONFIG_USB_NET_NET1080 is not set
+CONFIG_USB_NET_MCS7830=y
+# CONFIG_USB_NET_CDC_SUBSET is not set
+# CONFIG_USB_NET_ZAURUS is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_INTERRUPT=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_INPUT_GPIO=y
+CONFIG_INPUT_ALPS_GPIO_SCROLLWHEEL=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_TEGRA=y
+CONFIG_SENSORS_LM90=y
+CONFIG_MFD_MAX8907C=y
+CONFIG_MFD_TPS6586X=y
+CONFIG_MFD_TPS6591X=y
+CONFIG_MFD_TPS80031=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MAX8907C=y
+CONFIG_REGULATOR_TPS6586X=y
+CONFIG_REGULATOR_TPS6591X=y
+CONFIG_REGULATOR_TPS6236X=y
+CONFIG_REGULATOR_TPS80031=y
+CONFIG_REGULATOR_GPIO_SWITCH=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_VIDEO_DEV=y
+# CONFIG_MEDIA_TUNER_SIMPLE is not set
+# CONFIG_MEDIA_TUNER_TDA8290 is not set
+# CONFIG_MEDIA_TUNER_TDA827X is not set
+# CONFIG_MEDIA_TUNER_TDA18271 is not set
+# CONFIG_MEDIA_TUNER_TDA9887 is not set
+# CONFIG_MEDIA_TUNER_TEA5761 is not set
+# CONFIG_MEDIA_TUNER_TEA5767 is not set
+# CONFIG_MEDIA_TUNER_MT20XX is not set
+# CONFIG_MEDIA_TUNER_MT2060 is not set
+# CONFIG_MEDIA_TUNER_MT2266 is not set
+# CONFIG_MEDIA_TUNER_MT2131 is not set
+# CONFIG_MEDIA_TUNER_QT1010 is not set
+# CONFIG_MEDIA_TUNER_XC2028 is not set
+# CONFIG_MEDIA_TUNER_XC5000 is not set
+# CONFIG_MEDIA_TUNER_MXL5005S is not set
+# CONFIG_MEDIA_TUNER_MXL5007T is not set
+# CONFIG_MEDIA_TUNER_MC44S803 is not set
+# CONFIG_MEDIA_TUNER_MAX2165 is not set
+# CONFIG_MEDIA_TUNER_TDA18218 is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+# CONFIG_TEGRA_AVP is not set
+# CONFIG_TEGRA_MEDIASERVER is not set
+CONFIG_TEGRA_NVAVP=y
+CONFIG_VIDEO_OV5650=m
+CONFIG_VIDEO_OV2710=m
+CONFIG_TORCH_SSL3250A=m
+CONFIG_TORCH_TPS61050=m
+CONFIG_VIDEO_SH532U=m
+# CONFIG_V4L_USB_DRIVERS is not set
+# CONFIG_RADIO_ADAPTERS is not set
+CONFIG_FB=y
+CONFIG_TEGRA_GRHOST=y
+CONFIG_TEGRA_DC=y
+CONFIG_TEGRA_NVHDCP=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_TEGRA=y
+CONFIG_SND_SOC_TEGRA_WM8903=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_WHITELIST is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_LIBUSUAL=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_TEGRA_OTG=y
+CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_EMBEDDED_SDIO=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_TPS6591x=y
+CONFIG_RTC_DRV_TPS80031=y
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+CONFIG_IIO=y
+CONFIG_SENSORS_ISL29018=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=m
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_NTFS_FS=m
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_ROOT_NFS=y
+CONFIG_CIFS=m
+CONFIG_CIFS_EXPERIMENTAL=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_UTF8=m
+CONFIG_PRINTK_TIME=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+CONFIG_DEBUG_SLAB=y
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_VM=y
+CONFIG_DEBUG_SG=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_FUNCTION_TRACER=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_TEGRA_SE=y
+CONFIG_CRC_CCITT=y
index a2f2d27..2e5e33b 100644 (file)
@@ -191,6 +191,7 @@ CONFIG_APDS9802ALS=y
 CONFIG_SENSORS_NCT1008=y
 CONFIG_ISL29003=y
 CONFIG_SENSORS_AK8975=y
+CONFIG_SENSORS_NCT1008=y
 CONFIG_UID_STAT=y
 CONFIG_BCM4329_RFKILL=y
 CONFIG_TEGRA_CRYPTO_DEV=y
@@ -278,14 +279,15 @@ CONFIG_REGULATOR_TPS6586X=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_VIDEO_DEV=y
 CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-CONFIG_VIDEO_OV5650=y
-CONFIG_VIDEO_OV2710=y
-CONFIG_VIDEO_SOC380=y
-CONFIG_TORCH_SSL3250A=y
-CONFIG_VIDEO_SH532U=y
-CONFIG_VIDEO_AD5820=y
+CONFIG_VIDEO_OV5650=m
+CONFIG_VIDEO_OV2710=m
+CONFIG_VIDEO_SOC380=m
+CONFIG_TORCH_SSL3250A=m
+CONFIG_VIDEO_SH532U=m
+CONFIG_VIDEO_AD5820=m
 CONFIG_USB_VIDEO_CLASS=y
 # CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_VGA_ARB is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=y
 CONFIG_FB=y
 CONFIG_TEGRA_GRHOST=y
diff --git a/arch/arm/configs/tegra_p1852_gnu_linux_defconfig b/arch/arm/configs/tegra_p1852_gnu_linux_defconfig
new file mode 100644 (file)
index 0000000..3e8a44d
--- /dev/null
@@ -0,0 +1,227 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_CROSS_COMPILE="arm-eabi-"
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_PANIC_TIMEOUT=10
+CONFIG_EMBEDDED=y
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_ELF_CORE is not set
+CONFIG_ASHMEM=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_TEGRA=y
+CONFIG_ARCH_TEGRA_3x_SOC=y
+CONFIG_TEGRA_PCI=y
+CONFIG_MACH_P1852=y
+CONFIG_TEGRA_DEBUG_UARTB=y
+CONFIG_TEGRA_PWM=y
+# CONFIG_TEGRA_CPU_DVFS is not set
+CONFIG_TEGRA_CLOCK_DEBUG_WRITE=y
+CONFIG_TEGRA_MC_PROFILE=y
+CONFIG_ARM_ERRATA_743622=y
+CONFIG_ARM_ERRATA_751472=y
+CONFIG_ARM_ERRATA_752520=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_HIGHMEM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=448@2048M console=ttyS0,115200n8 earlyprintk init=/bin/ash"
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_INET_ESP=y
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_IPV6_TUNNEL=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+# CONFIG_ANDROID_PARANOID_NETWORK is not set
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_NOR_TEGRA=y
+CONFIG_MTD_NAND_TEGRA=y
+CONFIG_MTD_NAND=y
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_ANDROID_PMEM is not set
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=y
+CONFIG_DM_UEVENT=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_SMSC75XX=y
+CONFIG_USB_NET_SMSC95XX=y
+# CONFIG_USB_NET_NET1080 is not set
+# CONFIG_USB_NET_CDC_SUBSET is not set
+# CONFIG_USB_NET_ZAURUS is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_TEGRA=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_TEGRA=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_TEGRA=y
+CONFIG_SPI=y
+CONFIG_SPI_TEGRA=y
+CONFIG_SPI_SLAVE_TEGRA=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PDA_POWER=y
+CONFIG_BATTERY_BQ20Z75=y
+CONFIG_MFD_TPS6591X=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
+CONFIG_REGULATOR_TPS6591X=y
+CONFIG_REGULATOR_TPS6236X=y
+CONFIG_REGULATOR_GPIO_SWITCH=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_VIDEO_DEV=y
+# CONFIG_TEGRA_AVP is not set
+# CONFIG_TEGRA_MEDIASERVER is not set
+CONFIG_TEGRA_NVAVP=y
+# CONFIG_VGA_ARB is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+CONFIG_TEGRA_GRHOST=y
+CONFIG_TEGRA_DC=y
+CONFIG_TEGRA_DC_EXTENSIONS=y
+CONFIG_NVMAP_SEARCH_GLOBAL_HANDLES=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_TEGRA_ALSA=y
+CONFIG_SND_SOC_GENERIC_CODEC=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_STORAGE=y
+CONFIG_USB_LIBUSUAL=y
+CONFIG_USB_TEGRA_OTG=y
+CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_EMBEDDED_SDIO=y
+CONFIG_MMC_PARANOID_SD_INIT=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_MMC_BLOCK_DEFERRED_RESUME=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_SWITCH=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_TEGRA=y
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+CONFIG_IIO=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_ROOT_NFS=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_VM=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_ARM_UNWIND is not set
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_TWOFISH=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRC_CCITT=y
+CONFIG_LIBCRC32C=y
index 1ec30e9..d208fc0 100644 (file)
@@ -19,4 +19,4 @@
 #include <asm-generic/sizes.h>
 
 #define SZ_48M  (SZ_32M + SZ_16M)
-#define SZ_160M (SZ_128M | SZ_32M)
\ No newline at end of file
+#define SZ_160M (SZ_128M | SZ_32M)
index 54df114..0d2b3b0 100644 (file)
@@ -151,6 +151,13 @@ config MACH_TEGRA_ENTERPRISE
        help
          Support for NVIDIA Enterprise development platform
 
+config MACH_KAI
+       bool "Kai board"
+       depends on ARCH_TEGRA_3x_SOC
+       select MACH_HAS_SND_SOC_TEGRA_RT5640 if SND_SOC
+       help
+         Support for NVIDIA KAI development platform
+
 choice
        prompt "Tegra platform type"
        default TEGRA_SILICON_PLATFORM
index d28a72c..d6e6fbb 100644 (file)
@@ -158,6 +158,9 @@ obj-${CONFIG_MACH_CARDHU}               += board-cardhu-sensors.o
 obj-${CONFIG_MACH_CARDHU}               += board-cardhu-memory.o
 obj-${CONFIG_MACH_CARDHU}               += board-cardhu-powermon.o
 
+obj-${CONFIG_MACH_KAI}                  += board-touch-kai-synaptics-spi.o
+obj-${CONFIG_MACH_KAI}                  += board-touch-kai-raydium_spi.o
+
 obj-${CONFIG_MACH_TEGRA_ENTERPRISE}     += board-enterprise.o
 obj-${CONFIG_MACH_TEGRA_ENTERPRISE}     += board-enterprise-panel.o
 obj-${CONFIG_MACH_TEGRA_ENTERPRISE}     += board-enterprise-pinmux.o
@@ -168,6 +171,14 @@ obj-${CONFIG_MACH_TEGRA_ENTERPRISE}     += board-enterprise-baseband.o
 obj-${CONFIG_MACH_TEGRA_ENTERPRISE}     += board-enterprise-kbc.o
 obj-${CONFIG_MACH_TEGRA_ENTERPRISE}     += board-enterprise-sensors.o
 
+obj-${CONFIG_MACH_KAI}                  += board-kai.o
+obj-${CONFIG_MACH_KAI}                  += board-kai-kbc.o
+obj-${CONFIG_MACH_KAI}                  += board-kai-memory.o
+obj-${CONFIG_MACH_KAI}                  += board-kai-panel.o
+obj-${CONFIG_MACH_KAI}                  += board-kai-pinmux.o
+obj-${CONFIG_MACH_KAI}                  += board-kai-power.o
+obj-${CONFIG_MACH_KAI}                  += board-kai-sdhci.o
+
 obj-${CONFIG_TEGRA_BB_XMM_POWER}        += baseband-xmm-power.o
 obj-${CONFIG_TEGRA_BB_XMM_POWER2}       += baseband-xmm-power2.o
 
index 5455035..5d7958b 100644 (file)
@@ -28,6 +28,7 @@
 #include <linux/uaccess.h>
 #include <linux/wakelock.h>
 #include <linux/usb.h>
+#include <linux/pm_runtime.h>
 #include <mach/usb_phy.h>
 #include "board.h"
 #include "devices.h"
@@ -96,6 +97,8 @@ static struct usb_device *usbdev;
 static bool CP_initiated_L2toL0;
 static bool modem_power_on;
 static int power_onoff;
+static int reenable_autosuspend;
+static struct work_struct autopm_resume_work;
 static void baseband_xmm_power_L2_resume(void);
 
 static int baseband_modem_power_on(struct baseband_power_platform_data *data)
@@ -130,6 +133,8 @@ static int baseband_xmm_power_on(struct platform_device *device)
                pr_err("%s: !data\n", __func__);
                return -EINVAL;
        }
+       if (baseband_xmm_powerstate != BBXMM_PS_UNINIT)
+               return -EINVAL;
 
        /* reset the state machine */
        baseband_xmm_powerstate = BBXMM_PS_INIT;
@@ -177,6 +182,8 @@ static int baseband_xmm_power_off(struct platform_device *device)
 
        pr_debug("%s {\n", __func__);
 
+       if (baseband_xmm_powerstate == BBXMM_PS_UNINIT)
+               return -EINVAL;
        /* check for device / platform data */
        if (!device) {
                pr_err("%s: !device\n", __func__);
@@ -189,8 +196,9 @@ static int baseband_xmm_power_off(struct platform_device *device)
                return -EINVAL;
        }
 
+       ipc_ap_wake_state = IPC_AP_WAKE_UNINIT;
+
        /* unregister usb host controller */
-       pr_info("%s: hsic device: %x\n", __func__, data->modem.xmm.hsic_device);
        if (data->hsic_unregister)
                data->hsic_unregister(data->modem.xmm.hsic_device);
        else
@@ -207,6 +215,7 @@ static int baseband_xmm_power_off(struct platform_device *device)
        gpio_set_value(data->modem.xmm.bb_rst, 0);
        mdelay(1);
 
+       baseband_xmm_powerstate = BBXMM_PS_UNINIT;
        pr_debug("%s }\n", __func__);
 
        return 0;
@@ -384,6 +393,10 @@ irqreturn_t baseband_xmm_power_ipc_ap_wake_irq(int irq, void *dev_id)
                                                (baseband_power_driver_data->
                                                modem.xmm.ipc_bb_wake, 0);
                                        pr_debug("gpio slave wakeup done ->\n");
+                                       if ((reenable_autosuspend) && (usbdev)) {
+                                               reenable_autosuspend = false;
+                                               queue_work(workqueue, &autopm_resume_work);
+                                       }
                                }
                                baseband_xmm_set_power_status(BBXMM_PS_L0);
                        }
@@ -451,6 +464,22 @@ static void baseband_xmm_power_init2_work(struct work_struct *work)
 
 }
 
+static void baseband_xmm_power_autopm_resume(struct work_struct *work)
+{
+       struct usb_interface *intf;
+
+       pr_debug("%s\n", __func__);
+       if (usbdev) {
+
+               usb_lock_device(usbdev);
+               intf = usb_ifnum_to_if(usbdev, 0);
+               usb_autopm_get_interface(intf);
+               usb_autopm_put_interface(intf);
+               usb_unlock_device(usbdev);
+       }
+}
+
+
 /* Do the work for AP/CP initiated L2->L0 */
 static void baseband_xmm_power_L2_resume(void)
 {
@@ -667,7 +696,7 @@ static int baseband_xmm_power_driver_probe(struct platform_device *device)
        int err;
 
        pr_debug("%s\n", __func__);
-       pr_debug("[XMM] enum_delay_ms=%d\n", enum_delay_ms);
+       pr_debug("[XMM] enum_delay_ms=%ld\n", enum_delay_ms);
 
        /* check for platform data */
        if (!data)
@@ -757,6 +786,7 @@ static int baseband_xmm_power_driver_probe(struct platform_device *device)
        INIT_WORK(&init1_work, baseband_xmm_power_init1_work);
        INIT_WORK(&init2_work, baseband_xmm_power_init2_work);
        INIT_WORK(&L2_resume_work, baseband_xmm_power_L2_resume_work);
+       INIT_WORK(&autopm_resume_work, baseband_xmm_power_autopm_resume);
 
        /* init state variables */
        register_hsic_device = true;
@@ -838,7 +868,6 @@ static int baseband_xmm_power_driver_resume(struct platform_device *device)
        /* check if modem is on */
        if (power_onoff == 0) {
                pr_debug("%s - flight mode - nop\n", __func__);
-               baseband_xmm_set_power_status(BBXMM_PS_L3TOL0);
                return 0;
        }
 
@@ -861,6 +890,7 @@ static int baseband_xmm_power_driver_resume(struct platform_device *device)
        } else {
                pr_info("CP L3 -> L0\n");
        }
+       reenable_autosuspend = true;
 
        return 0;
 }
index dd05202..77ba073 100644 (file)
@@ -611,7 +611,10 @@ static int baseband_xmm_power2_driver_remove(struct platform_device *device)
        }
 
        /* free work structure */
-       destroy_workqueue(workqueue);
+       if (workqueue) {
+               cancel_work_sync(baseband_xmm_power2_work);
+               destroy_workqueue(workqueue);
+       }
        kfree(baseband_xmm_power2_work);
        baseband_xmm_power2_work = (struct baseband_xmm_power_work_t *) 0;
 
index b64a453..90801b0 100644 (file)
@@ -942,6 +942,8 @@ static struct tegra_dc_out cardhu_disp1_out = {
        .parent_clk     = "pll_p",
 
 #ifndef CONFIG_TEGRA_CARDHU_DSI
+       .parent_clk_backup = "pll_d2_out0",
+
        .type           = TEGRA_DC_OUT_RGB,
        .depth          = 18,
        .dither         = TEGRA_DC_ORDERED_DITHER,
@@ -1074,7 +1076,7 @@ static struct ion_platform_data tegra_ion_data = {
                        .name = "iommu",
                        .base = TEGRA_SMMU_BASE,
                        .size = TEGRA_SMMU_SIZE,
-                       .dev = &tegra_iommu_device.dev,
+                       .priv = &tegra_iommu_device.dev,
                },
        },
 };
index c969337..b1dd860 100644 (file)
@@ -655,7 +655,7 @@ static struct i2c_board_info cardhu_i2c4_nct1008_board_info[] = {
 static int cardhu_nct1008_init(void)
 {
        int nct1008_port = -1;
-       int ret;
+       int ret = 0;
 
        if ((board_info.board_id == BOARD_E1198) ||
                (board_info.board_id == BOARD_E1291) ||
index bea6a6f..5b0f0d8 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/board-cardhu.c
  *
- * Copyright (c) 2011, NVIDIA Corporation.
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -184,10 +184,10 @@ static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
        { "i2s1",       "pll_a_out0",   0,              false},
        { "i2s3",       "pll_a_out0",   0,              false},
        { "spdif_out",  "pll_a_out0",   0,              false},
-       { "d_audio",    "pll_a_out0",   0,              false},
-       { "dam0",       "pll_a_out0",   0,              false},
-       { "dam1",       "pll_a_out0",   0,              false},
-       { "dam2",       "pll_a_out0",   0,              false},
+       { "d_audio",    "clk_m",        12000000,       false},
+       { "dam0",       "clk_m",        12000000,       false},
+       { "dam1",       "clk_m",        12000000,       false},
+       { "dam2",       "clk_m",        12000000,       false},
        { "audio1",     "i2s1_sync",    0,              false},
        { "audio3",     "i2s3_sync",    0,              false},
        { "vi_sensor",  "pll_p",        150000000,      false},
@@ -346,6 +346,8 @@ static void __init uart_debug_init(void)
                        (board_info.board_id == BOARD_E1257))
                                debug_port_id = 1;
        }
+
+       tegra_init_debug_uart_rate();
        switch (debug_port_id) {
        case 0:
                /* UARTA is the debug port. */
@@ -1011,14 +1013,6 @@ static void __init tegra_cardhu_init(void)
 #endif
 }
 
-static void __init cardhu_ramconsole_reserve(unsigned long size)
-{
-       struct resource *res;
-       long ret;
-
-       tegra_ram_console_debug_reserve(SZ_1M);
-}
-
 static void __init tegra_cardhu_reserve(void)
 {
 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
@@ -1027,7 +1021,7 @@ static void __init tegra_cardhu_reserve(void)
 #else
        tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
 #endif
-       cardhu_ramconsole_reserve(SZ_1M);
+       tegra_ram_console_debug_reserve(SZ_1M);
 }
 
 MACHINE_START(CARDHU, "cardhu")
index a94eb40..ec7eae3 100644 (file)
@@ -722,9 +722,14 @@ static void enterprise_panel_early_suspend(struct early_suspend *h)
 #ifdef CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND
        cpufreq_save_default_governor();
        cpufreq_set_conservative_governor();
-       cpufreq_set_conservative_governor_param(
-               SET_CONSERVATIVE_GOVERNOR_UP_THRESHOLD,
-               SET_CONSERVATIVE_GOVERNOR_DOWN_THRESHOLD);
+       cpufreq_set_conservative_governor_param("up_threshold",
+                       SET_CONSERVATIVE_GOVERNOR_UP_THRESHOLD);
+
+       cpufreq_set_conservative_governor_param("down_threshold",
+                       SET_CONSERVATIVE_GOVERNOR_DOWN_THRESHOLD);
+
+       cpufreq_set_conservative_governor_param("freq_step",
+                       SET_CONSERVATIVE_GOVERNOR_FREQ_STEP);
 #endif
 }
 
index fbdfa5b..3a6ea00 100644 (file)
@@ -30,6 +30,8 @@
 #include <linux/io.h>
 #include <linux/cpumask.h>
 #include <linux/platform_data/tegra_bpc_mgmt.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/gpio-regulator.h>
 
 #include <mach/edp.h>
 #include <mach/iomap.h>
@@ -356,7 +358,7 @@ static struct regulator_consumer_supply fixed_reg_vdd_fuse_en_supply[] = {
 };
 
 /* LCD-D17 (GPIO M1) from T30*/
-static struct regulator_consumer_supply fixed_reg_sdmmc3_vdd_sel_supply[] = {
+static struct regulator_consumer_supply gpio_reg_sdmmc3_vdd_sel_supply[] = {
        REGULATOR_SUPPLY("vddio_sdmmc3_2v85_1v8", NULL),
        REGULATOR_SUPPLY("sdmmc3_compu_pu", NULL),
        REGULATOR_SUPPLY("vddio_sdmmc3", NULL),
@@ -399,6 +401,70 @@ static struct regulator_consumer_supply fixed_reg_cam_ldo_1v8_en_supply[] = {
        REGULATOR_SUPPLY("vdd", "7-0036"),
 };
 
+static struct gpio_regulator_state gpio_reg_sdmmc3_vdd_sel_states[] = {
+       {
+               .gpios = 0,
+               .value = 2850000,
+       },
+       {
+               .gpios = 1,
+               .value = 1800000,
+       },
+};
+
+static struct gpio gpio_reg_sdmmc3_vdd_sel_gpios[] = {
+       {
+               .gpio = TEGRA_GPIO_PM1,
+               .flags = 0,
+               .label = "sdmmc3_vdd_sel",
+       },
+};
+
+/* Macro for defining gpio regulator device data */
+#define GPIO_REG(_id, _name, _input_supply, _active_high,              \
+       _boot_state, _delay_us, _minmv, _maxmv)                         \
+       static struct regulator_init_data ri_data_##_name =             \
+       {                                                               \
+               .supply_regulator = _input_supply,                      \
+               .num_consumer_supplies =                                \
+                       ARRAY_SIZE(gpio_reg_##_name##_supply),          \
+               .consumer_supplies = gpio_reg_##_name##_supply,         \
+               .constraints = {                                        \
+                       .name = "gpio_reg_"#_name,                      \
+                       .min_uV = (_minmv)*1000,                        \
+                       .max_uV = (_maxmv)*1000,                        \
+                       .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
+                                       REGULATOR_MODE_STANDBY),        \
+                       .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
+                                       REGULATOR_CHANGE_STATUS |       \
+                                       REGULATOR_CHANGE_VOLTAGE),      \
+               },                                                      \
+       };                                                              \
+       static struct gpio_regulator_config gpio_reg_##_name##_pdata =  \
+       {                                                               \
+               .supply_name = _input_supply,                           \
+               .enable_gpio = -EINVAL,                                 \
+               .enable_high = _active_high,                            \
+               .enabled_at_boot = _boot_state,                         \
+               .startup_delay = _delay_us,                             \
+               .gpios = gpio_reg_##_name##_gpios,                      \
+               .nr_gpios = ARRAY_SIZE(gpio_reg_##_name##_gpios),       \
+               .states = gpio_reg_##_name##_states,                    \
+               .nr_states = ARRAY_SIZE(gpio_reg_##_name##_states),     \
+               .type = REGULATOR_VOLTAGE,                              \
+               .init_data = &ri_data_##_name,                          \
+       };                                                              \
+       static struct platform_device gpio_reg_##_name##_dev = {        \
+               .name   = "gpio-regulator",                             \
+               .id = _id,                                              \
+               .dev    = {                                             \
+                       .platform_data = &gpio_reg_##_name##_pdata,     \
+               },                                                      \
+       }
+
+GPIO_REG(4, sdmmc3_vdd_sel,  tps80031_rails(SMPS4),
+               true, false, 0, 1000, 3300);
+
 /* Macro for defining fixed regulator sub device data */
 #define FIXED_REG(_id, _name, _input_supply, _gpio_nr, _active_high,   \
                        _millivolts, _boot_state)                       \
@@ -441,8 +507,6 @@ FIXED_REG(2, pmu_hdmi_5v0_en, "fixed_reg_pmu_5v15_en",
                ENT_TPS80031_GPIO_SYSEN, true, 5000, 0);
 FIXED_REG(3, vdd_fuse_en,     "fixed_reg_pmu_3v3_en",
                TEGRA_GPIO_PM0, true, 3300, 0);
-FIXED_REG(4, sdmmc3_vdd_sel,  tps80031_rails(SMPS4),
-               TEGRA_GPIO_PM1, true, 2850, 0);
 FIXED_REG(5, cam_ldo_2v8_en,  NULL,
                TEGRA_GPIO_PM7, true, 2800, 0);
 FIXED_REG(6, cam_ldo_1v8_en,  NULL,
@@ -454,16 +518,18 @@ static struct platform_device *fixed_regs_devices[] = {
        ADD_FIXED_REG(pmu_3v3_en),
        ADD_FIXED_REG(pmu_hdmi_5v0_en),
        ADD_FIXED_REG(vdd_fuse_en),
-       ADD_FIXED_REG(sdmmc3_vdd_sel),
        ADD_FIXED_REG(cam_ldo_2v8_en),
        ADD_FIXED_REG(cam_ldo_1v8_en),
 };
 
+#define ADD_GPIO_REG(_name) (&gpio_reg_##_name##_dev)
+static struct platform_device *gpio_regs_devices[] = {
+       ADD_GPIO_REG(sdmmc3_vdd_sel),
+};
+
 static int __init enterprise_fixed_regulator_init(void)
 {
        int i;
-       if (!is_enterprise_machine)
-               return 0;
 
        for (i = 0; i < ARRAY_SIZE(fixed_regs_devices); ++i) {
                struct fixed_voltage_config *fixed_reg_pdata =
@@ -474,7 +540,38 @@ static int __init enterprise_fixed_regulator_init(void)
        return platform_add_devices(fixed_regs_devices,
                                ARRAY_SIZE(fixed_regs_devices));
 }
-subsys_initcall_sync(enterprise_fixed_regulator_init);
+
+static int __init enterprise_gpio_regulator_init(void)
+{
+       int i, j;
+
+       for (i = 0; i < ARRAY_SIZE(gpio_regs_devices); ++i) {
+               struct gpio_regulator_config *gpio_reg_pdata =
+                       gpio_regs_devices[i]->dev.platform_data;
+               for (j = 0; j < gpio_reg_pdata->nr_gpios; ++j) {
+                       if (gpio_reg_pdata->gpios[j].gpio < TEGRA_NR_GPIOS)
+                               tegra_gpio_enable(gpio_reg_pdata->gpios[j].gpio);
+               }
+       }
+       return platform_add_devices(gpio_regs_devices,
+                                   ARRAY_SIZE(gpio_regs_devices));
+}
+
+static int __init enterprise_regulators_fixed_gpio_init(void)
+{
+       int ret;
+
+       if (!is_enterprise_machine)
+               return 0;
+
+       ret = enterprise_fixed_regulator_init();
+       if (ret)
+               return ret;
+
+       ret = enterprise_gpio_regulator_init();
+       return ret;
+}
+subsys_initcall_sync(enterprise_regulators_fixed_gpio_init);
 
 static void enterprise_power_off(void)
 {
index f631c9b..8c194b5 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/board-enterprise.c
  *
- * Copyright (c) 2011, NVIDIA Corporation.
+ * Copyright (c) 2011-2012, NVIDIA Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -177,17 +177,15 @@ static __initdata struct tegra_clk_init_table enterprise_clk_init_table[] = {
        { "hda2codec_2x","pll_p",       48000000,       false},
        { "pwm",        "clk_32k",      32768,          false},
        { "blink",      "clk_32k",      32768,          true},
-       { "pll_a",      NULL,           564480000,      false},
-       { "pll_a_out0", NULL,           11289600,       false},
        { "i2s0",       "pll_a_out0",   0,              false},
        { "i2s1",       "pll_a_out0",   0,              false},
        { "i2s2",       "pll_a_out0",   0,              false},
        { "i2s3",       "pll_a_out0",   0,              false},
        { "spdif_out",  "pll_a_out0",   0,              false},
-       { "d_audio",    "pll_a_out0",   0,              false},
-       { "dam0",       "pll_a_out0",   0,              false},
-       { "dam1",       "pll_a_out0",   0,              false},
-       { "dam2",       "pll_a_out0",   0,              false},
+       { "d_audio",    "clk_m",        12000000,       false},
+       { "dam0",       "clk_m",        12000000,       false},
+       { "dam1",       "clk_m",        12000000,       false},
+       { "dam2",       "clk_m",        12000000,       false},
        { "audio0",     "i2s0_sync",    0,              false},
        { "audio1",     "i2s1_sync",    0,              false},
        { "audio2",     "i2s2_sync",    0,              false},
@@ -395,6 +393,8 @@ static void __init uart_debug_init(void)
        unsigned long rate;
        struct clk *c;
 
+       tegra_init_debug_uart_rate();
+
        /* UARTD is the debug port. */
        pr_info("Selecting UARTD as the debug console\n");
        enterprise_uart_devices[3] = &debug_uartd_device;
@@ -956,14 +956,6 @@ static void __init tegra_enterprise_init(void)
        enterprise_nfc_init();
 }
 
-static void __init tegra_enterprise_ramconsole_reserve(unsigned long size)
-{
-       struct resource *res;
-       long ret;
-
-       tegra_ram_console_debug_reserve(SZ_1M);
-}
-
 static void __init tegra_enterprise_reserve(void)
 {
 #if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
@@ -971,7 +963,7 @@ static void __init tegra_enterprise_reserve(void)
 #else
        tegra_reserve(SZ_128M, SZ_4M, SZ_8M);
 #endif
-       tegra_enterprise_ramconsole_reserve(SZ_1M);
+       tegra_ram_console_debug_reserve(SZ_1M);
 }
 
 MACHINE_START(TEGRA_ENTERPRISE, "tegra_enterprise")
index a841b37..7d29a9c 100644 (file)
@@ -312,6 +312,7 @@ static struct tegra_suspend_platform_data harmony_suspend_data = {
 int __init harmony_suspend_init(void)
 {
        tegra_init_suspend(&harmony_suspend_data);
+       return 0;
 }
 
 int __init harmony_regulator_init(void)
diff --git a/arch/arm/mach-tegra/board-kai-kbc.c b/arch/arm/mach-tegra/board-kai-kbc.c
new file mode 100644 (file)
index 0000000..704789d
--- /dev/null
@@ -0,0 +1,115 @@
+/*
+ * arch/arm/mach-tegra/board-kai-kbc.c
+ * Keys configuration for Nvidia tegra3 kai platform.
+ *
+ * Copyright (C) 2012 NVIDIA, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/device.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/interrupt_keys.h>
+#include <linux/gpio_scrollwheel.h>
+
+#include <mach/irqs.h>
+#include <mach/io.h>
+#include <mach/iomap.h>
+#include <mach/kbc.h>
+#include "board.h"
+#include "board-kai.h"
+
+#include "gpio-names.h"
+#include "devices.h"
+
+#define GPIO_KEY(_id, _gpio, _iswake)          \
+       {                                       \
+               .code = _id,                    \
+               .gpio = TEGRA_GPIO_##_gpio,     \
+               .active_low = 1,                \
+               .desc = #_id,                   \
+               .type = EV_KEY,                 \
+               .wakeup = _iswake,              \
+               .debounce_interval = 10,        \
+       }
+
+static struct gpio_keys_button kai_keys[] = {
+       [0] = GPIO_KEY(KEY_MENU, PR2, 0),
+       [1] = GPIO_KEY(KEY_BACK, PQ1, 0),
+       [2] = GPIO_KEY(KEY_HOME, PQ0, 0),
+       [3] = GPIO_KEY(KEY_SEARCH, PQ3, 0),
+       [4] = GPIO_KEY(KEY_VOLUMEUP, PR1, 0),
+       [5] = GPIO_KEY(KEY_VOLUMEDOWN, PR0, 0),
+};
+
+static struct gpio_keys_platform_data kai_keys_platform_data = {
+       .buttons        = kai_keys,
+       .nbuttons       = ARRAY_SIZE(kai_keys),
+};
+
+static struct platform_device kai_keys_device = {
+       .name   = "gpio-keys",
+       .id     = 0,
+       .dev    = {
+               .platform_data  = &kai_keys_platform_data,
+       },
+};
+
+#define INT_KEY(_id, _irq, _iswake, _deb_int)  \
+       {                                       \
+               .code = _id,                    \
+               .irq = _irq,                    \
+               .active_low = 1,                \
+               .desc = #_id,                   \
+               .type = EV_KEY,                 \
+               .wakeup = _iswake,              \
+               .debounce_interval = _deb_int,  \
+       }
+static struct interrupt_keys_button kai_int_keys[] = {
+};
+
+static struct interrupt_keys_platform_data kai_int_keys_pdata = {
+       .int_buttons    = kai_int_keys,
+       .nbuttons       = ARRAY_SIZE(kai_int_keys),
+};
+
+static struct platform_device kai_int_keys_device = {
+       .name   = "interrupt-keys",
+       .id     = 0,
+       .dev    = {
+               .platform_data  = &kai_int_keys_pdata,
+       },
+};
+
+int __init kai_keys_init(void)
+{
+       int i;
+
+       pr_info("Registering gpio keys\n");
+
+       /* Enable gpio mode for other pins */
+       for (i = 0; i < kai_keys_platform_data.nbuttons; i++)
+               tegra_gpio_enable(kai_keys_platform_data.
+                                       buttons[i].gpio);
+
+       platform_device_register(&kai_keys_device);
+       platform_device_register(&kai_int_keys_device);
+
+       return 0;
+}
diff --git a/arch/arm/mach-tegra/board-kai-memory.c b/arch/arm/mach-tegra/board-kai-memory.c
new file mode 100644 (file)
index 0000000..0e300d6
--- /dev/null
@@ -0,0 +1,757 @@
+/*
+ * Copyright (C) 2011 NVIDIA, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "board.h"
+#include "board-kai.h"
+#include "tegra3_emc.h"
+#include "fuse.h"
+
+
+static const struct tegra_emc_table kai_emc_tables_h5tc4g[] = {
+       {
+               0x32,       /* Rev 3.2 */
+               25500,      /* SDRAM frequency */
+               {
+                       0x00000001, /* EMC_RC */
+                       0x00000007, /* EMC_RFC */
+                       0x00000000, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000002, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000005, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_QUSE */
+                       0x00000004, /* EMC_QRST */
+                       0x00000009, /* EMC_QSAFE */
+                       0x0000000b, /* EMC_RDV */
+                       0x000000c0, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000030, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000008, /* EMC_TXSR */
+                       0x00000008, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000002, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x000000c7, /* EMC_TREFBW */
+                       0x00000006, /* EMC_QUSE_EXTRA */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00004288, /* EMC_FBIO_CFG5 */
+                       0x007800a4, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS3 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS4 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS5 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS6 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000002a0, /* EMC_XM2CMDPADCTRL */
+                       0x0800211c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77fff884, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x05057404, /* EMC_XM2VTTGENPADCTRL */
+                       0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x08000168, /* EMC_XM2QUSEPADCTRL */
+                       0x08000000, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000040, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000287, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00020001, /* MC_EMEM_ARB_CFG */
+                       0xc0000008, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06020102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0502, /* MC_EMEM_ARB_DA_COVERS */
+                       0x75e30303, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0xe8000000, /* EMC_FBIO_SPARE */
+                       0xff00ff00, /* EMC_CFG_RSV */
+               },
+               0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000001, /* EMC_CFG.PERIODIC_QRST */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000001, /* EMC_CFG.DYN_SELF_REF */
+       },
+       {
+               0x32,       /* Rev 3.2 */
+               51000,      /* SDRAM frequency */
+               {
+                       0x00000002, /* EMC_RC */
+                       0x0000000f, /* EMC_RFC */
+                       0x00000001, /* EMC_RAS */
+                       0x00000000, /* EMC_RP */
+                       0x00000002, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000005, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000000, /* EMC_RD_RCD */
+                       0x00000000, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_QUSE */
+                       0x00000004, /* EMC_QRST */
+                       0x00000009, /* EMC_QSAFE */
+                       0x0000000b, /* EMC_RDV */
+                       0x00000181, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000010, /* EMC_TXSR */
+                       0x00000010, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000003, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x0000018e, /* EMC_TREFBW */
+                       0x00000006, /* EMC_QUSE_EXTRA */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00004288, /* EMC_FBIO_CFG5 */
+                       0x007800a4, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS3 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS4 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS5 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS6 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000002a0, /* EMC_XM2CMDPADCTRL */
+                       0x0800211c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77fff884, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x05057404, /* EMC_XM2VTTGENPADCTRL */
+                       0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x08000168, /* EMC_XM2QUSEPADCTRL */
+                       0x08000000, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000040, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00010001, /* MC_EMEM_ARB_CFG */
+                       0xc000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06020102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0502, /* MC_EMEM_ARB_DA_COVERS */
+                       0x74e30303, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0xe8000000, /* EMC_FBIO_SPARE */
+                       0xff00ff00, /* EMC_CFG_RSV */
+               },
+               0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000001, /* EMC_CFG.PERIODIC_QRST */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000001, /* EMC_CFG.DYN_SELF_REF */
+       },
+       {
+               0x32,       /* Rev 3.2 */
+               102000,     /* SDRAM frequency */
+               {
+                       0x00000005, /* EMC_RC */
+                       0x0000001e, /* EMC_RFC */
+                       0x00000003, /* EMC_RAS */
+                       0x00000001, /* EMC_RP */
+                       0x00000002, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000005, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000001, /* EMC_RD_RCD */
+                       0x00000001, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_QUSE */
+                       0x00000004, /* EMC_QRST */
+                       0x00000009, /* EMC_QSAFE */
+                       0x0000000b, /* EMC_RDV */
+                       0x00000303, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000020, /* EMC_TXSR */
+                       0x00000020, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x00000005, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x0000031c, /* EMC_TREFBW */
+                       0x00000006, /* EMC_QUSE_EXTRA */
+                       0x00000004, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00004288, /* EMC_FBIO_CFG5 */
+                       0x007800a4, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS3 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS4 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS5 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS6 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+                       0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000002a0, /* EMC_XM2CMDPADCTRL */
+                       0x0800211c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77fff884, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x05057404, /* EMC_XM2VTTGENPADCTRL */
+                       0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x08000168, /* EMC_XM2QUSEPADCTRL */
+                       0x08000000, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00000000, /* EMC_ZCAL_INTERVAL */
+                       0x00000040, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00000001, /* MC_EMEM_ARB_CFG */
+                       0xc0000013, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06020102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0503, /* MC_EMEM_ARB_DA_COVERS */
+                       0x74430504, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0xe8000000, /* EMC_FBIO_SPARE */
+                       0xff00ff00, /* EMC_CFG_RSV */
+               },
+               0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000001, /* EMC_CFG.PERIODIC_QRST */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000001, /* EMC_CFG.DYN_SELF_REF */
+       },
+       {
+               0x32,       /* Rev 3.2 */
+               204000,     /* SDRAM frequency */
+               {
+                       0x0000000a, /* EMC_RC */
+                       0x0000003d, /* EMC_RFC */
+                       0x00000007, /* EMC_RAS */
+                       0x00000002, /* EMC_RP */
+                       0x00000002, /* EMC_R2W */
+                       0x0000000a, /* EMC_W2R */
+                       0x00000005, /* EMC_R2P */
+                       0x0000000b, /* EMC_W2P */
+                       0x00000002, /* EMC_RD_RCD */
+                       0x00000002, /* EMC_WR_RCD */
+                       0x00000003, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000005, /* EMC_WDV */
+                       0x00000005, /* EMC_QUSE */
+                       0x00000004, /* EMC_QRST */
+                       0x00000009, /* EMC_QSAFE */
+                       0x0000000b, /* EMC_RDV */
+                       0x00000607, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x00000002, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000f, /* EMC_RW2PDEN */
+                       0x00000040, /* EMC_TXSR */
+                       0x00000040, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x0000000a, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000638, /* EMC_TREFBW */
+                       0x00000006, /* EMC_QUSE_EXTRA */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00004288, /* EMC_FBIO_CFG5 */
+                       0x004400a4, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00080000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00080000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00080000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00080000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00080000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00080000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00080000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00080000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00080000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000002a0, /* EMC_XM2CMDPADCTRL */
+                       0x0800211c, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77fff884, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f108, /* EMC_XM2COMPPADCTRL */
+                       0x05057404, /* EMC_XM2VTTGENPADCTRL */
+                       0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x08000168, /* EMC_XM2QUSEPADCTRL */
+                       0x08000000, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x000c000c, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00000003, /* MC_EMEM_ARB_CFG */
+                       0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06020102, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000a0505, /* MC_EMEM_ARB_DA_COVERS */
+                       0x74040a06, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0xe8000000, /* EMC_FBIO_SPARE */
+                       0xff00ff00, /* EMC_CFG_RSV */
+               },
+               0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000001, /* EMC_CFG.PERIODIC_QRST */
+               0x80001221, /* Mode Register 0 */
+               0x80100003, /* Mode Register 1 */
+               0x80200008, /* Mode Register 2 */
+               0x00000001, /* EMC_CFG.DYN_SELF_REF */
+       },
+       {
+               0x32,       /* Rev 3.2 */
+               333500,     /* SDRAM frequency */
+               {
+                       0x0000000f, /* EMC_RC */
+                       0x00000063, /* EMC_RFC */
+                       0x0000000a, /* EMC_RAS */
+                       0x00000003, /* EMC_RP */
+                       0x00000003, /* EMC_R2W */
+                       0x00000008, /* EMC_W2R */
+                       0x00000002, /* EMC_R2P */
+                       0x00000009, /* EMC_W2P */
+                       0x00000003, /* EMC_RD_RCD */
+                       0x00000003, /* EMC_WR_RCD */
+                       0x00000002, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000004, /* EMC_WDV */
+                       0x00000006, /* EMC_QUSE */
+                       0x00000004, /* EMC_QRST */
+                       0x0000000a, /* EMC_QSAFE */
+                       0x0000000c, /* EMC_RDV */
+                       0x000009e9, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x0000027a, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000001, /* EMC_PDEX2WR */
+                       0x00000008, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x00000007, /* EMC_AR2PDEN */
+                       0x0000000e, /* EMC_RW2PDEN */
+                       0x00000068, /* EMC_TXSR */
+                       0x00000200, /* EMC_TXSRDLL */
+                       0x00000004, /* EMC_TCKE */
+                       0x0000000f, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000004, /* EMC_TCLKSTABLE */
+                       0x00000005, /* EMC_TCLKSTOP */
+                       0x00000a2a, /* EMC_TREFBW */
+                       0x00000000, /* EMC_QUSE_EXTRA */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00007088, /* EMC_FBIO_CFG5 */
+                       0x002600a4, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00014000, /* EMC_DLL_XFORM_DQS0 */
+                       0x00014000, /* EMC_DLL_XFORM_DQS1 */
+                       0x00014000, /* EMC_DLL_XFORM_DQS2 */
+                       0x00014000, /* EMC_DLL_XFORM_DQS3 */
+                       0x00014000, /* EMC_DLL_XFORM_DQS4 */
+                       0x00014000, /* EMC_DLL_XFORM_DQS5 */
+                       0x00014000, /* EMC_DLL_XFORM_DQS6 */
+                       0x00014000, /* EMC_DLL_XFORM_DQS7 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x00020000, /* EMC_DLL_XFORM_DQ0 */
+                       0x00020000, /* EMC_DLL_XFORM_DQ1 */
+                       0x00020000, /* EMC_DLL_XFORM_DQ2 */
+                       0x00020000, /* EMC_DLL_XFORM_DQ3 */
+                       0x000002a0, /* EMC_XM2CMDPADCTRL */
+                       0x0800013d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77fff884, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f508, /* EMC_XM2COMPPADCTRL */
+                       0x05057404, /* EMC_XM2VTTGENPADCTRL */
+                       0x54000007, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x080001e8, /* EMC_XM2QUSEPADCTRL */
+                       0x08000021, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x015c000c, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10000, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x800014d4, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x00000005, /* MC_EMEM_ARB_CFG */
+                       0x8000003d, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_RC */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x06030202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x000b0608, /* MC_EMEM_ARB_DA_COVERS */
+                       0x70850f09, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0xe8000000, /* EMC_FBIO_SPARE */
+                       0xff00ff89, /* EMC_CFG_RSV */
+               },
+               0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000000, /* EMC_CFG.PERIODIC_QRST */
+               0x80000321, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200000, /* Mode Register 2 */
+               0x00000000, /* EMC_CFG.DYN_SELF_REF */
+       },
+       {
+               0x32,       /* Rev 3.2 */
+               667000,     /* SDRAM frequency */
+               {
+                       0x00000020, /* EMC_RC */
+                       0x000000c7, /* EMC_RFC */
+                       0x00000017, /* EMC_RAS */
+                       0x00000007, /* EMC_RP */
+                       0x00000005, /* EMC_R2W */
+                       0x0000000c, /* EMC_W2R */
+                       0x00000003, /* EMC_R2P */
+                       0x00000011, /* EMC_W2P */
+                       0x00000007, /* EMC_RD_RCD */
+                       0x00000007, /* EMC_WR_RCD */
+                       0x00000002, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000007, /* EMC_WDV */
+                       0x0000000a, /* EMC_QUSE */
+                       0x00000009, /* EMC_QRST */
+                       0x0000000d, /* EMC_QSAFE */
+                       0x00000012, /* EMC_RDV */
+                       0x00001412, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x00000504, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000002, /* EMC_PDEX2WR */
+                       0x0000000e, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x0000000c, /* EMC_AR2PDEN */
+                       0x00000016, /* EMC_RW2PDEN */
+                       0x000000cf, /* EMC_TXSR */
+                       0x00000200, /* EMC_TXSRDLL */
+                       0x00000005, /* EMC_TCKE */
+                       0x0000001f, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000006, /* EMC_TCLKSTABLE */
+                       0x00000007, /* EMC_TCLKSTOP */
+                       0x00001453, /* EMC_TREFBW */
+                       0x0000000b, /* EMC_QUSE_EXTRA */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x00000000, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00005088, /* EMC_FBIO_CFG5 */
+                       0xf00b0191, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS2 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS4 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS5 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS6 */
+                       0x0000000a, /* EMC_DLL_XFORM_DQS7 */
+                       0x00018000, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00018000, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00018000, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00018000, /* EMC_DLL_XFORM_QUSE3 */
+                       0x00018000, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00018000, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00018000, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00018000, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ0 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ1 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ2 */
+                       0x0000000c, /* EMC_DLL_XFORM_DQ3 */
+                       0x000002a0, /* EMC_XM2CMDPADCTRL */
+                       0x0600013d, /* EMC_XM2DQSPADCTRL2 */
+                       0x22220000, /* EMC_XM2DQPADCTRL2 */
+                       0x77fff884, /* EMC_XM2CLKPADCTRL */
+                       0x01f1f501, /* EMC_XM2COMPPADCTRL */
+                       0x07077404, /* EMC_XM2VTTGENPADCTRL */
+                       0x54000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x080001e8, /* EMC_XM2QUSEPADCTRL */
+                       0x06000021, /* EMC_XM2DQSPADCTRL3 */
+                       0x00000802, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000100, /* EMC_ZCAL_WAIT_CNT */
+                       0x00f8000c, /* EMC_MRS_WAIT_CNT */
+                       0xa0f10202, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_CTT */
+                       0x00000000, /* EMC_CTT_DURATION */
+                       0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x0000000a, /* MC_EMEM_ARB_CFG */
+                       0x80000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000010, /* MC_EMEM_ARB_TIMING_RC */
+                       0x0000000b, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x08040202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x00130b10, /* MC_EMEM_ARB_DA_COVERS */
+                       0x70ea1f11, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+                       0xe8000000, /* EMC_FBIO_SPARE */
+                       0xff00ff49, /* EMC_CFG_RSV */
+               },
+               0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x00000001, /* EMC_CFG.PERIODIC_QRST */
+               0x80000b71, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200018, /* Mode Register 2 */
+               0x00000000, /* EMC_CFG.DYN_SELF_REF */
+       },
+};
+
+int kai_emc_init(void)
+{
+       tegra_init_emc(kai_emc_tables_h5tc4g,
+                      ARRAY_SIZE(kai_emc_tables_h5tc4g));
+
+       return 0;
+}
diff --git a/arch/arm/mach-tegra/board-kai-panel.c b/arch/arm/mach-tegra/board-kai-panel.c
new file mode 100644 (file)
index 0000000..86a1555
--- /dev/null
@@ -0,0 +1,703 @@
+/*
+ * arch/arm/mach-tegra/board-kai-panel.c
+ *
+ * Copyright (c) 2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/resource.h>
+#include <asm/mach-types.h>
+#include <linux/platform_device.h>
+#include <linux/earlysuspend.h>
+#include <linux/pwm_backlight.h>
+#include <asm/atomic.h>
+#include <linux/nvhost.h>
+#include <mach/nvmap.h>
+#include <mach/irqs.h>
+#include <mach/iomap.h>
+#include <mach/dc.h>
+#include <mach/fb.h>
+
+#include "board.h"
+#include "board-kai.h"
+#include "devices.h"
+#include "gpio-names.h"
+
+/* kai default display board pins */
+#define kai_lvds_avdd_en               TEGRA_GPIO_PH6
+#define kai_lvds_stdby                 TEGRA_GPIO_PG5
+#define kai_lvds_rst                   TEGRA_GPIO_PG7
+#define kai_lvds_shutdown              TEGRA_GPIO_PN6
+#define kai_lvds_rs                    TEGRA_GPIO_PH1
+#define kai_lvds_lr                    TEGRA_GPIO_PG1
+
+/* common pins( backlight ) for all display boards */
+#define kai_bl_enb                     TEGRA_GPIO_PH3
+#define kai_bl_pwm                     TEGRA_GPIO_PH0
+#define kai_hdmi_hpd                   TEGRA_GPIO_PN7
+
+#ifdef CONFIG_TEGRA_DC
+static struct regulator *kai_hdmi_reg;
+static struct regulator *kai_hdmi_pll;
+static struct regulator *kai_hdmi_vddio;
+#endif
+
+static atomic_t sd_brightness = ATOMIC_INIT(255);
+
+static struct regulator *kai_lvds_reg;
+static struct regulator *kai_lvds_vdd_panel;
+
+static tegra_dc_bl_output kai_bl_output_measured = {
+       0, 1, 2, 3, 4, 5, 6, 7,
+       8, 9, 10, 11, 12, 13, 14, 15,
+       16, 17, 18, 19, 20, 21, 22, 23,
+       24, 25, 26, 27, 28, 29, 30, 31,
+       32, 33, 34, 35, 36, 37, 38, 39,
+       40, 41, 42, 43, 44, 45, 46, 47,
+       48, 49, 49, 50, 51, 52, 53, 54,
+       55, 56, 57, 58, 59, 60, 61, 62,
+       63, 64, 65, 66, 67, 68, 69, 70,
+       70, 72, 73, 74, 75, 76, 77, 78,
+       79, 80, 81, 82, 83, 84, 85, 86,
+       87, 88, 89, 90, 91, 92, 93, 94,
+       95, 96, 97, 98, 99, 100, 101, 102,
+       103, 104, 105, 106, 107, 108, 110, 111,
+       112, 113, 114, 115, 116, 117, 118, 119,
+       120, 121, 122, 123, 124, 124, 125, 126,
+       127, 128, 129, 130, 131, 132, 133, 133,
+       134, 135, 136, 137, 138, 139, 140, 141,
+       142, 143, 144, 145, 146, 147, 148, 148,
+       149, 150, 151, 152, 153, 154, 155, 156,
+       157, 158, 159, 160, 161, 162, 163, 164,
+       165, 166, 167, 168, 169, 170, 171, 172,
+       173, 174, 175, 176, 177, 179, 180, 181,
+       182, 184, 185, 186, 187, 188, 189, 190,
+       191, 192, 193, 194, 195, 196, 197, 198,
+       199, 200, 201, 202, 203, 204, 205, 206,
+       207, 208, 209, 211, 212, 213, 214, 215,
+       216, 217, 218, 219, 220, 221, 222, 223,
+       224, 225, 226, 227, 228, 229, 230, 231,
+       232, 233, 234, 235, 236, 237, 238, 239,
+       240, 241, 242, 243, 244, 245, 246, 247,
+       248, 249, 250, 251, 252, 253, 254, 255
+};
+
+static p_tegra_dc_bl_output bl_output;
+
+static int kai_backlight_init(struct device *dev)
+{
+       int ret;
+
+       bl_output = kai_bl_output_measured;
+
+       if (WARN_ON(ARRAY_SIZE(kai_bl_output_measured) != 256))
+               pr_err("bl_output array does not have 256 elements\n");
+
+       tegra_gpio_disable(kai_bl_pwm);
+
+       ret = gpio_request(kai_bl_enb, "backlight_enb");
+       if (ret < 0)
+               return ret;
+
+       ret = gpio_direction_output(kai_bl_enb, 1);
+       if (ret < 0)
+               gpio_free(kai_bl_enb);
+       else
+               tegra_gpio_enable(kai_bl_enb);
+
+       return ret;
+};
+
+static void kai_backlight_exit(struct device *dev)
+{
+       /* int ret; */
+       /*ret = gpio_request(kai_bl_enb, "backlight_enb");*/
+       gpio_set_value(kai_bl_enb, 0);
+       gpio_free(kai_bl_enb);
+       tegra_gpio_disable(kai_bl_enb);
+       return;
+}
+
+static int kai_backlight_notify(struct device *unused, int brightness)
+{
+       int cur_sd_brightness = atomic_read(&sd_brightness);
+
+       /* Set the backlight GPIO pin mode to 'backlight_enable' */
+       gpio_set_value(kai_bl_enb, !!brightness);
+
+       /* SD brightness is a percentage, 8-bit value. */
+       brightness = (brightness * cur_sd_brightness) / 255;
+
+       /* Apply any backlight response curve */
+       if (brightness > 255)
+               pr_info("Error: Brightness > 255!\n");
+       else
+               brightness = bl_output[brightness];
+
+       return brightness;
+}
+
+static int kai_disp1_check_fb(struct device *dev, struct fb_info *info);
+
+static struct platform_pwm_backlight_data kai_backlight_data = {
+       .pwm_id         = 0,
+       .max_brightness = 255,
+       .dft_brightness = 224,
+       .pwm_period_ns  = 100000,
+       .init           = kai_backlight_init,
+       .exit           = kai_backlight_exit,
+       .notify         = kai_backlight_notify,
+       /* Only toggle backlight on fb blank notifications for disp1 */
+       .check_fb       = kai_disp1_check_fb,
+};
+
+static struct platform_device kai_backlight_device = {
+       .name   = "pwm-backlight",
+       .id     = -1,
+       .dev    = {
+               .platform_data = &kai_backlight_data,
+       },
+};
+
+static int kai_panel_enable(void)
+{
+       if (kai_lvds_reg == NULL) {
+               kai_lvds_reg = regulator_get(NULL, "vdd_lvds");
+               if (WARN_ON(IS_ERR(kai_lvds_reg)))
+                       pr_err("%s: couldn't get regulator vdd_lvds: %ld\n",
+                              __func__, PTR_ERR(kai_lvds_reg));
+               else
+                       regulator_enable(kai_lvds_reg);
+       }
+
+       if (kai_lvds_vdd_panel == NULL) {
+               kai_lvds_vdd_panel = regulator_get(NULL, "vdd_lcd_panel");
+               if (WARN_ON(IS_ERR(kai_lvds_vdd_panel)))
+                       pr_err("%s: couldn't get regulator vdd_lcd_panel: %ld\n",
+                              __func__, PTR_ERR(kai_lvds_vdd_panel));
+               else
+                       regulator_enable(kai_lvds_vdd_panel);
+       }
+
+       mdelay(5);
+
+       gpio_set_value(kai_lvds_avdd_en, 1);
+       mdelay(5);
+
+       gpio_set_value(kai_lvds_stdby, 1);
+       gpio_set_value(kai_lvds_rst, 1);
+       gpio_set_value(kai_lvds_shutdown, 1);
+       gpio_set_value(kai_lvds_lr, 1);
+
+       mdelay(10);
+
+       return 0;
+}
+
+static int kai_panel_disable(void)
+{
+       gpio_set_value(kai_lvds_lr, 0);
+       gpio_set_value(kai_lvds_shutdown, 0);
+       gpio_set_value(kai_lvds_rst, 0);
+       gpio_set_value(kai_lvds_stdby, 0);
+       mdelay(5);
+
+       gpio_set_value(kai_lvds_avdd_en, 0);
+       mdelay(5);
+
+       regulator_disable(kai_lvds_reg);
+       regulator_put(kai_lvds_reg);
+       kai_lvds_reg = NULL;
+
+       regulator_disable(kai_lvds_vdd_panel);
+       regulator_put(kai_lvds_vdd_panel);
+       kai_lvds_vdd_panel = NULL;
+
+       return 0;
+}
+
+#ifdef CONFIG_TEGRA_DC
+static int kai_hdmi_vddio_enable(void)
+{
+       int ret;
+       if (!kai_hdmi_vddio) {
+               kai_hdmi_vddio = regulator_get(NULL, "vdd_hdmi_con");
+               if (IS_ERR_OR_NULL(kai_hdmi_vddio)) {
+                       ret = PTR_ERR(kai_hdmi_vddio);
+                       pr_err("hdmi: couldn't get regulator vdd_hdmi_con\n");
+                       kai_hdmi_vddio = NULL;
+                       return ret;
+               }
+       }
+       ret = regulator_enable(kai_hdmi_vddio);
+       if (ret < 0) {
+               pr_err("hdmi: couldn't enable regulator vdd_hdmi_con\n");
+               regulator_put(kai_hdmi_vddio);
+               kai_hdmi_vddio = NULL;
+               return ret;
+       }
+       return ret;
+}
+
+static int kai_hdmi_vddio_disable(void)
+{
+       if (kai_hdmi_vddio) {
+               regulator_disable(kai_hdmi_vddio);
+               regulator_put(kai_hdmi_vddio);
+               kai_hdmi_vddio = NULL;
+       }
+       return 0;
+}
+
+static int kai_hdmi_enable(void)
+{
+       int ret;
+       if (!kai_hdmi_reg) {
+               kai_hdmi_reg = regulator_get(NULL, "avdd_hdmi");
+               if (IS_ERR_OR_NULL(kai_hdmi_reg)) {
+                       pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
+                       kai_hdmi_reg = NULL;
+                       return PTR_ERR(kai_hdmi_reg);
+               }
+       }
+       ret = regulator_enable(kai_hdmi_reg);
+       if (ret < 0) {
+               pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
+               return ret;
+       }
+       if (!kai_hdmi_pll) {
+               kai_hdmi_pll = regulator_get(NULL, "avdd_hdmi_pll");
+               if (IS_ERR_OR_NULL(kai_hdmi_pll)) {
+                       pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
+                       kai_hdmi_pll = NULL;
+                       regulator_put(kai_hdmi_reg);
+                       kai_hdmi_reg = NULL;
+                       return PTR_ERR(kai_hdmi_pll);
+               }
+       }
+       ret = regulator_enable(kai_hdmi_pll);
+       if (ret < 0) {
+               pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
+               return ret;
+       }
+       return 0;
+}
+
+static int kai_hdmi_disable(void)
+{
+       regulator_disable(kai_hdmi_reg);
+       regulator_put(kai_hdmi_reg);
+       kai_hdmi_reg = NULL;
+
+       regulator_disable(kai_hdmi_pll);
+       regulator_put(kai_hdmi_pll);
+       kai_hdmi_pll = NULL;
+       return 0;
+}
+
+static struct resource kai_disp1_resources[] = {
+       {
+               .name   = "irq",
+               .start  = INT_DISPLAY_GENERAL,
+               .end    = INT_DISPLAY_GENERAL,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               .name   = "regs",
+               .start  = TEGRA_DISPLAY_BASE,
+               .end    = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "fbmem",
+               .start  = 0,    /* Filled in by kai_panel_init() */
+               .end    = 0,    /* Filled in by kai_panel_init() */
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct resource kai_disp2_resources[] = {
+       {
+               .name   = "irq",
+               .start  = INT_DISPLAY_B_GENERAL,
+               .end    = INT_DISPLAY_B_GENERAL,
+               .flags  = IORESOURCE_IRQ,
+       },
+       {
+               .name   = "regs",
+               .start  = TEGRA_DISPLAY2_BASE,
+               .end    = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+       {
+               .name   = "fbmem",
+               .flags  = IORESOURCE_MEM,
+               .start  = 0,
+               .end    = 0,
+       },
+       {
+               .name   = "hdmi_regs",
+               .start  = TEGRA_HDMI_BASE,
+               .end    = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+#endif
+
+static struct tegra_dc_mode kai_panel_modes[] = {
+       {
+               /* 1024x600@60Hz */
+               .pclk = 51206000,
+               .h_ref_to_sync = 11,
+               .v_ref_to_sync = 1,
+               .h_sync_width = 10,
+               .v_sync_width = 5,
+               .h_back_porch = 10,
+               .v_back_porch = 15,
+               .h_active = 1024,
+               .v_active = 600,
+               .h_front_porch = 300,
+               .v_front_porch = 15,
+       },
+};
+
+static struct tegra_dc_sd_settings kai_sd_settings = {
+       .enable = 1, /* enabled by default. */
+       .use_auto_pwm = false,
+       .hw_update_delay = 0,
+       .bin_width = -1,
+       .aggressiveness = 1,
+       .phase_in_adjustments = true,
+       .use_vid_luma = false,
+       /* Default video coefficients */
+       .coeff = {5, 9, 2},
+       .fc = {0, 0},
+       /* Immediate backlight changes */
+       .blp = {1024, 255},
+       /* Gammas: R: 2.2 G: 2.2 B: 2.2 */
+       /* Default BL TF */
+       .bltf = {
+                       {
+                               {57, 65, 74, 83},
+                               {93, 103, 114, 126},
+                               {138, 151, 165, 179},
+                               {194, 209, 225, 242},
+                       },
+                       {
+                               {58, 66, 75, 84},
+                               {94, 105, 116, 127},
+                               {140, 153, 166, 181},
+                               {196, 211, 227, 244},
+                       },
+                       {
+                               {60, 68, 77, 87},
+                               {97, 107, 119, 130},
+                               {143, 156, 170, 184},
+                               {199, 215, 231, 248},
+                       },
+                       {
+                               {64, 73, 82, 91},
+                               {102, 113, 124, 137},
+                               {149, 163, 177, 192},
+                               {207, 223, 240, 255},
+                       },
+               },
+       /* Default LUT */
+       .lut = {
+                       {
+                               {250, 250, 250},
+                               {194, 194, 194},
+                               {149, 149, 149},
+                               {113, 113, 113},
+                               {82, 82, 82},
+                               {56, 56, 56},
+                               {34, 34, 34},
+                               {15, 15, 15},
+                               {0, 0, 0},
+                       },
+                       {
+                               {246, 246, 246},
+                               {191, 191, 191},
+                               {147, 147, 147},
+                               {111, 111, 111},
+                               {80, 80, 80},
+                               {55, 55, 55},
+                               {33, 33, 33},
+                               {14, 14, 14},
+                               {0, 0, 0},
+                       },
+                       {
+                               {239, 239, 239},
+                               {185, 185, 185},
+                               {142, 142, 142},
+                               {107, 107, 107},
+                               {77, 77, 77},
+                               {52, 52, 52},
+                               {30, 30, 30},
+                               {12, 12, 12},
+                               {0, 0, 0},
+                       },
+                       {
+                               {224, 224, 224},
+                               {173, 173, 173},
+                               {133, 133, 133},
+                               {99, 99, 99},
+                               {70, 70, 70},
+                               {46, 46, 46},
+                               {25, 25, 25},
+                               {7, 7, 7},
+                               {0, 0, 0},
+                       },
+               },
+       .sd_brightness = &sd_brightness,
+       .bl_device = &kai_backlight_device,
+};
+
+#ifdef CONFIG_TEGRA_DC
+static struct tegra_fb_data kai_fb_data = {
+       .win            = 0,
+       .xres           = 1024,
+       .yres           = 600,
+       .bits_per_pixel = 32,
+       .flags          = TEGRA_FB_FLIP_ON_PROBE,
+};
+
+static struct tegra_fb_data kai_hdmi_fb_data = {
+       .win            = 0,
+       .xres           = 1024,
+       .yres           = 600,
+       .bits_per_pixel = 32,
+       .flags          = TEGRA_FB_FLIP_ON_PROBE,
+};
+
+static struct tegra_dc_out kai_disp2_out = {
+       .type           = TEGRA_DC_OUT_HDMI,
+       .flags          = TEGRA_DC_OUT_HOTPLUG_HIGH,
+
+       .dcc_bus        = 3,
+       .hotplug_gpio   = kai_hdmi_hpd,
+
+       .max_pixclock   = KHZ2PICOS(148500),
+
+       .align          = TEGRA_DC_ALIGN_MSB,
+       .order          = TEGRA_DC_ORDER_RED_BLUE,
+
+       .enable         = kai_hdmi_enable,
+       .disable        = kai_hdmi_disable,
+
+       .postsuspend    = kai_hdmi_vddio_disable,
+       .hotplug_init   = kai_hdmi_vddio_enable,
+};
+
+static struct tegra_dc_platform_data kai_disp2_pdata = {
+       .flags          = 0,
+       .default_out    = &kai_disp2_out,
+       .fb             = &kai_hdmi_fb_data,
+       .emc_clk_rate   = 300000000,
+};
+#endif
+
+static struct tegra_dc_out kai_disp1_out = {
+       .align          = TEGRA_DC_ALIGN_MSB,
+       .order          = TEGRA_DC_ORDER_RED_BLUE,
+       .sd_settings    = &kai_sd_settings,
+       .parent_clk     = "pll_p",
+
+       .type           = TEGRA_DC_OUT_RGB,
+       .depth          = 18,
+       .dither         = TEGRA_DC_ORDERED_DITHER,
+
+       .modes          = kai_panel_modes,
+       .n_modes        = ARRAY_SIZE(kai_panel_modes),
+
+       .enable         = kai_panel_enable,
+       .disable        = kai_panel_disable,
+};
+
+#ifdef CONFIG_TEGRA_DC
+static struct tegra_dc_platform_data kai_disp1_pdata = {
+       .flags          = TEGRA_DC_FLAG_ENABLED,
+       .default_out    = &kai_disp1_out,
+       .emc_clk_rate   = 300000000,
+       .fb             = &kai_fb_data,
+};
+
+static struct nvhost_device kai_disp1_device = {
+       .name           = "tegradc",
+       .id             = 0,
+       .resource       = kai_disp1_resources,
+       .num_resources  = ARRAY_SIZE(kai_disp1_resources),
+       .dev = {
+               .platform_data = &kai_disp1_pdata,
+       },
+};
+
+static int kai_disp1_check_fb(struct device *dev, struct fb_info *info)
+{
+       return info->device == &kai_disp1_device.dev;
+}
+
+static struct nvhost_device kai_disp2_device = {
+       .name           = "tegradc",
+       .id             = 1,
+       .resource       = kai_disp2_resources,
+       .num_resources  = ARRAY_SIZE(kai_disp2_resources),
+       .dev = {
+               .platform_data = &kai_disp2_pdata,
+       },
+};
+#else
+static int kai_disp1_check_fb(struct device *dev, struct fb_info *info)
+{
+       return 0;
+}
+#endif
+
+static struct nvmap_platform_carveout kai_carveouts[] = {
+       [0] = NVMAP_HEAP_CARVEOUT_IRAM_INIT,
+       [1] = {
+               .name           = "generic-0",
+               .usage_mask     = NVMAP_HEAP_CARVEOUT_GENERIC,
+               .base           = 0,    /* Filled in by kai_panel_init() */
+               .size           = 0,    /* Filled in by kai_panel_init() */
+               .buddy_size     = SZ_32K,
+       },
+};
+
+static struct nvmap_platform_data kai_nvmap_data = {
+       .carveouts      = kai_carveouts,
+       .nr_carveouts   = ARRAY_SIZE(kai_carveouts),
+};
+
+static struct platform_device kai_nvmap_device = {
+       .name   = "tegra-nvmap",
+       .id     = -1,
+       .dev    = {
+               .platform_data = &kai_nvmap_data,
+       },
+};
+
+
+static struct platform_device *kai_gfx_devices[] __initdata = {
+       &kai_nvmap_device,
+#ifdef CONFIG_TEGRA_GRHOST
+       &tegra_grhost_device,
+#endif
+       &tegra_pwfm0_device,
+       &kai_backlight_device,
+};
+
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+/* put early_suspend/late_resume handlers here for the display in order
+ * to keep the code out of the display driver, keeping it closer to upstream
+ */
+struct early_suspend kai_panel_early_suspender;
+
+static void kai_panel_early_suspend(struct early_suspend *h)
+{
+       /* power down LCD, add use a black screen for HDMI */
+       if (num_registered_fb > 0)
+               fb_blank(registered_fb[0], FB_BLANK_POWERDOWN);
+       if (num_registered_fb > 1)
+               fb_blank(registered_fb[1], FB_BLANK_NORMAL);
+}
+
+static void kai_panel_late_resume(struct early_suspend *h)
+{
+       unsigned i;
+       for (i = 0; i < num_registered_fb; i++)
+               fb_blank(registered_fb[i], FB_BLANK_UNBLANK);
+}
+#endif
+
+int __init kai_panel_init(void)
+{
+       int err;
+       struct resource __maybe_unused *res;
+
+       kai_carveouts[1].base = tegra_carveout_start;
+       kai_carveouts[1].size = tegra_carveout_size;
+
+       gpio_request(kai_lvds_avdd_en, "lvds_avdd_en");
+       gpio_direction_output(kai_lvds_avdd_en, 1);
+       tegra_gpio_enable(kai_lvds_avdd_en);
+
+       gpio_request(kai_lvds_stdby, "lvds_stdby");
+       gpio_direction_output(kai_lvds_stdby, 1);
+       tegra_gpio_enable(kai_lvds_stdby);
+
+       gpio_request(kai_lvds_rst, "lvds_rst");
+       gpio_direction_output(kai_lvds_rst, 1);
+       tegra_gpio_enable(kai_lvds_rst);
+
+       gpio_request(kai_lvds_rs, "lvds_rs");
+       gpio_direction_output(kai_lvds_rs, 0);
+       tegra_gpio_enable(kai_lvds_rs);
+
+       gpio_request(kai_lvds_lr, "lvds_lr");
+       gpio_direction_output(kai_lvds_lr, 1);
+       tegra_gpio_enable(kai_lvds_lr);
+
+       gpio_request(kai_lvds_shutdown, "lvds_shutdown");
+       gpio_direction_output(kai_lvds_shutdown, 1);
+       tegra_gpio_enable(kai_lvds_shutdown);
+
+       tegra_gpio_enable(kai_hdmi_hpd);
+       gpio_request(kai_hdmi_hpd, "hdmi_hpd");
+       gpio_direction_input(kai_hdmi_hpd);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+       kai_panel_early_suspender.suspend = kai_panel_early_suspend;
+       kai_panel_early_suspender.resume = kai_panel_late_resume;
+       kai_panel_early_suspender.level = EARLY_SUSPEND_LEVEL_DISABLE_FB;
+       register_early_suspend(&kai_panel_early_suspender);
+#endif
+
+       err = platform_add_devices(kai_gfx_devices,
+                               ARRAY_SIZE(kai_gfx_devices));
+
+#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC)
+       res = nvhost_get_resource_byname(&kai_disp1_device,
+                                        IORESOURCE_MEM, "fbmem");
+       res->start = tegra_fb_start;
+       res->end = tegra_fb_start + tegra_fb_size - 1;
+#endif
+
+       /* Copy the bootloader fb to the fb. */
+       tegra_move_framebuffer(tegra_fb_start, tegra_bootloader_fb_start,
+                               min(tegra_fb_size, tegra_bootloader_fb_size));
+
+#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC)
+       if (!err)
+               err = nvhost_device_register(&kai_disp1_device);
+
+       res = nvhost_get_resource_byname(&kai_disp2_device,
+                                        IORESOURCE_MEM, "fbmem");
+       res->start = tegra_fb2_start;
+       res->end = tegra_fb2_start + tegra_fb2_size - 1;
+       if (!err)
+               err = nvhost_device_register(&kai_disp2_device);
+#endif
+
+#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_NVAVP)
+       if (!err)
+               err = nvhost_device_register(&nvavp_device);
+#endif
+       return err;
+}
diff --git a/arch/arm/mach-tegra/board-kai-pinmux.c b/arch/arm/mach-tegra/board-kai-pinmux.c
new file mode 100644 (file)
index 0000000..2288003
--- /dev/null
@@ -0,0 +1,550 @@
+/*
+ * arch/arm/mach-tegra/board-kai-pinmux.c
+ *
+ * Copyright (C) 2012 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <mach/pinmux.h>
+#include "board.h"
+#include "board-kai.h"
+#include "gpio-names.h"
+
+#define DEFAULT_DRIVE(_name)                                   \
+       {                                                       \
+               .pingroup = TEGRA_DRIVE_PINGROUP_##_name,       \
+               .hsm = TEGRA_HSM_DISABLE,                       \
+               .schmitt = TEGRA_SCHMITT_ENABLE,                \
+               .drive = TEGRA_DRIVE_DIV_1,                     \
+               .pull_down = TEGRA_PULL_31,                     \
+               .pull_up = TEGRA_PULL_31,                       \
+               .slew_rising = TEGRA_SLEW_SLOWEST,              \
+               .slew_falling = TEGRA_SLEW_SLOWEST,             \
+       }
+/* Setting the drive strength of pins
+ * hsm: Enable High speed mode (ENABLE/DISABLE)
+ * Schimit: Enable/disable schimit (ENABLE/DISABLE)
+ * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
+ * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
+ *                strength code. Value from 0 to 31.
+ * pullup_drive - drive up (rising edge)  - Driver Output Pull-Up drive
+ *                strength code. Value from 0 to 31.
+ * pulldn_slew -  Driver Output Pull-Up slew control code  - 2bit code
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ * pullup_slew -  Driver Output Pull-Down slew control code -
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ */
+#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \
+       {                                               \
+               .pingroup = TEGRA_DRIVE_PINGROUP_##_name,   \
+               .hsm = TEGRA_HSM_##_hsm,                    \
+               .schmitt = TEGRA_SCHMITT_##_schmitt,        \
+               .drive = TEGRA_DRIVE_##_drive,              \
+               .pull_down = TEGRA_PULL_##_pulldn_drive,    \
+               .pull_up = TEGRA_PULL_##_pullup_drive,          \
+               .slew_rising = TEGRA_SLEW_##_pulldn_slew,   \
+               .slew_falling = TEGRA_SLEW_##_pullup_slew,      \
+       }
+
+/* !!!FIXME!!!! POPULATE THIS TABLE */
+static __initdata struct tegra_drive_pingroup_config kai_drive_pinmux[] = {
+       /* DEFAULT_DRIVE(<pin_group>), */
+       /* SET_DRIVE(ATA, DISABLE, DISABLE, DIV_1, 31, 31, FAST, FAST) */
+       SET_DRIVE(DAP2,         DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+       /* All I2C pins are driven to maximum drive strength */
+       /* GEN1 I2C */
+       SET_DRIVE(DBG,          DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+       /* GEN2 I2C */
+       SET_DRIVE(AT5,          DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+       /* CAM I2C */
+       SET_DRIVE(GME,          DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+       /* DDC I2C */
+       SET_DRIVE(DDC,          DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+       /* PWR_I2C */
+       SET_DRIVE(AO1,          DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+       /* UART3 */
+       SET_DRIVE(UART3,        DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST),
+
+       /* SDMMC1 */
+       SET_DRIVE(SDIO1,        DISABLE, DISABLE, DIV_1, 46, 42, FAST, FAST),
+
+       /* SDMMC3 */
+       SET_DRIVE(SDIO3,        DISABLE, DISABLE, DIV_1, 46, 42, FAST, FAST),
+
+       /* SDMMC4 */
+       SET_DRIVE(GMA,          DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
+       SET_DRIVE(GMB,          DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
+       SET_DRIVE(GMC,          DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
+       SET_DRIVE(GMD,          DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST),
+
+};
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io)      \
+       {                                                       \
+               .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
+               .func           = TEGRA_MUX_##_mux,             \
+               .pupd           = TEGRA_PUPD_##_pupd,           \
+               .tristate       = TEGRA_TRI_##_tri,             \
+               .io             = TEGRA_PIN_##_io,              \
+               .lock           = TEGRA_PIN_LOCK_DEFAULT,       \
+               .od             = TEGRA_PIN_OD_DEFAULT,         \
+               .ioreset        = TEGRA_PIN_IO_RESET_DEFAULT,   \
+       }
+
+#define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \
+       {                                                       \
+               .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
+               .func           = TEGRA_MUX_##_mux,             \
+               .pupd           = TEGRA_PUPD_##_pupd,           \
+               .tristate       = TEGRA_TRI_##_tri,             \
+               .io             = TEGRA_PIN_##_io,              \
+               .lock           = TEGRA_PIN_LOCK_##_lock,       \
+               .od             = TEGRA_PIN_OD_##_od,           \
+               .ioreset        = TEGRA_PIN_IO_RESET_DEFAULT,   \
+       }
+
+#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \
+       {                                                       \
+               .pingroup       = TEGRA_PINGROUP_##_pingroup,   \
+               .func           = TEGRA_MUX_##_mux,             \
+               .pupd           = TEGRA_PUPD_##_pupd,           \
+               .tristate       = TEGRA_TRI_##_tri,             \
+               .io             = TEGRA_PIN_##_io,              \
+               .lock           = TEGRA_PIN_LOCK_##_lock,       \
+               .od             = TEGRA_PIN_OD_DEFAULT,         \
+               .ioreset        = TEGRA_PIN_IO_RESET_##_ioreset \
+       }
+
+static __initdata struct tegra_pingroup_config kai_pinmux_common[] = {
+       /* SDMMC1 pinmux */
+       DEFAULT_PINMUX(SDMMC1_CLK,      SDMMC1,          NORMAL,     NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_CMD,      SDMMC1,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT3,     SDMMC1,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT2,     SDMMC1,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT1,     SDMMC1,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT0,     SDMMC1,          PULL_UP,    NORMAL,     INPUT),
+
+       /* SDMMC3 pinmux */
+       DEFAULT_PINMUX(SDMMC3_CLK,      SDMMC3,          NORMAL,     NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_CMD,      SDMMC3,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT0,     SDMMC3,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT1,     SDMMC3,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT2,     SDMMC3,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT3,     SDMMC3,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT6,     SDMMC3,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT7,     SDMMC3,          PULL_UP,    NORMAL,     INPUT),
+
+       /* SDMMC4 pinmux */
+       DEFAULT_PINMUX(SDMMC4_CLK,      SDMMC4,          NORMAL,     NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_CMD,      SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT0,     SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT1,     SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT2,     SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT3,     SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT4,     SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT5,     SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT6,     SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_DAT7,     SDMMC4,          PULL_UP,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SDMMC4_RST_N,    RSVD1,           PULL_DOWN,  NORMAL,     INPUT),
+
+       /* I2C1 pinmux */
+       I2C_PINMUX(GEN1_I2C_SCL,        I2C1,           NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+       I2C_PINMUX(GEN1_I2C_SDA,        I2C1,           NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+
+       /* I2C2 pinmux */
+       I2C_PINMUX(GEN2_I2C_SCL,        I2C2,           NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+       I2C_PINMUX(GEN2_I2C_SDA,        I2C2,           NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+
+       /* I2C3 pinmux */
+       I2C_PINMUX(CAM_I2C_SCL,         I2C3,           NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+       I2C_PINMUX(CAM_I2C_SDA,         I2C3,           NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+
+       /* I2C4 pinmux */
+       I2C_PINMUX(DDC_SCL,             I2C4,           NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+       I2C_PINMUX(DDC_SDA,             I2C4,           NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+
+       /* Power I2C pinmux */
+       I2C_PINMUX(PWR_I2C_SCL,         I2CPWR,         NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+       I2C_PINMUX(PWR_I2C_SDA,         I2CPWR,         NORMAL, NORMAL, INPUT,  DISABLE,        ENABLE),
+
+       /* LCD */
+       DEFAULT_PINMUX(LCD_PCLK,        DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_DE,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_HSYNC,       DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_VSYNC,       DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D0,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D1,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D2,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D3,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D4,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D5,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D6,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D7,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D8,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D9,          DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D10,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D11,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D12,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D13,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D14,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D15,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D16,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D17,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D18,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D19,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D20,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D21,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D22,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_D23,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+
+       /* UART B : GPS */
+       DEFAULT_PINMUX(UART2_RXD,       IRDA,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(UART2_TXD,       IRDA,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(UART2_RTS_N,     UARTB,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(UART2_CTS_N,     UARTB,           NORMAL,    NORMAL,     INPUT),
+
+       /*UART C : BT */
+       DEFAULT_PINMUX(UART3_TXD,       UARTC,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(UART3_RXD,       UARTC,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(UART3_CTS_N,     UARTC,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(UART3_RTS_N,     UARTC,           NORMAL,    NORMAL,     OUTPUT),
+
+       /* UART D : DEBUG */
+       DEFAULT_PINMUX(GMI_A16,         UARTD,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_A17,         UARTD,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_A18,         UARTD,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_A19,         UARTD,           NORMAL,    NORMAL,     OUTPUT),
+
+       /*  KBC keys */
+       DEFAULT_PINMUX(KB_COL0,         KBC,             PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL1,         KBC,             PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL2,         KBC,             PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_COL3,         KBC,             PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW0,         KBC,             PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW1,         KBC,             PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW2,         KBC,             PULL_UP,   NORMAL,     INPUT),
+
+       /* I2S0 : for MODEM */
+       DEFAULT_PINMUX(DAP1_FS,         I2S0,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP1_DIN,        I2S0,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP1_DOUT,       I2S0,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP1_SCLK,       I2S0,            NORMAL,    NORMAL,     INPUT),
+
+       /* I2S1 : for CODEC */
+       DEFAULT_PINMUX(DAP2_FS,         I2S1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP2_DIN,        I2S1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP2_DOUT,       I2S1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP2_SCLK,       I2S1,            NORMAL,    NORMAL,     INPUT),
+
+       /* I2S3 : for BT */
+       DEFAULT_PINMUX(DAP4_FS,         I2S3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP4_DIN,        I2S3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP4_DOUT,       I2S3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(DAP4_SCLK,       I2S3,            NORMAL,    NORMAL,     INPUT),
+
+       /* SPI1 : touch */
+       DEFAULT_PINMUX(SPI1_MOSI,       SPI1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI1_SCK,        SPI1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI1_CS0_N,      SPI1,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI1_MISO,       SPI1,            NORMAL,    NORMAL,     INPUT),
+
+       /* SPIDIF */
+       DEFAULT_PINMUX(SPDIF_IN,        SPDIF,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPDIF_OUT,       SPDIF,           NORMAL,    NORMAL,     OUTPUT),
+
+       /* FIXED FUNCTION AND CONFIGURATION */
+       DEFAULT_PINMUX(CLK_32K_OUT,     BLINK,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(SYS_CLK_REQ,     SYSCLK,          NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(OWR,             OWR,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_AD4,         RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CLK1_OUT,        EXTPERIPH1,      NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CLK2_OUT,        EXTPERIPH2,      NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CLK3_OUT,        EXTPERIPH3,      NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(CLK2_REQ,        DAP,             NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(HDMI_INT,        RSVD0,           NORMAL,    TRISTATE,   INPUT),
+
+       /* GPIO */
+       /* POWER RAIL GPIO */
+       DEFAULT_PINMUX(DAP3_FS,         I2S2,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD14,        RSVD1,           PULL_DOWN, NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT5,     SDMMC3,          NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(KB_ROW6,         KBC,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(KB_ROW7,         KBC,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(LCD_M1,          DISPLAYA,        NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(LCD_PWR0,        DISPLAYA,        NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(LCD_PWR1,        DISPLAYA,        NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(LCD_PWR2,        DISPLAYA,        NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(KB_ROW8,         KBC,             NORMAL,    NORMAL,     OUTPUT),
+
+       /* CAMERA */
+       DEFAULT_PINMUX(CAM_MCLK,        VI_ALT2,         PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PCC1,       RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB0,       RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB3,       VGP3,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB5,       VGP5,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB6,       VGP6,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PBB7,       I2S4,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PCC2,       I2S4,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW4,         KBC,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(KB_ROW5,         KBC,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(KB_ROW9,         KBC,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(KB_ROW10,        KBC,             NORMAL,    NORMAL,     OUTPUT),
+
+       /* MODEM */
+       DEFAULT_PINMUX(GPIO_PV0,        RSVD,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PV1,        RSVD,            NORMAL,    NORMAL,     INPUT),
+
+       /* GPS and BT */
+       DEFAULT_PINMUX(GPIO_PU0,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PU1,        RSVD1,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GPIO_PU2,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PU3,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PU4,        PWM1,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GPIO_PU5,        PWM2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GPIO_PU6,        RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(KB_ROW14,        KBC,             NORMAL,    TRISTATE,   OUTPUT),
+
+       /* LCD GPIO */
+       DEFAULT_PINMUX(GMI_AD0,         RSVD1,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD1,         RSVD1,           NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD2,         RSVD1,           PULL_DOWN, NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD3,         RSVD1,           PULL_DOWN, NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD5,         RSVD1,           PULL_DOWN, NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD6,         RSVD1,           PULL_DOWN, NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD7,         RSVD1,           PULL_DOWN, NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD8,         PWM0,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD9,         RSVD2,           PULL_DOWN, NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_AD11,        PWM3,            NORMAL,    NORMAL,     OUTPUT),
+
+       /* TOUCH */
+       DEFAULT_PINMUX(GMI_WAIT,        RSVD1,           PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_WP_N,        RSVD1,           PULL_UP,   NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_SDOUT,       DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_DC1,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_WR_N,        DISPLAYA,        PULL_UP,   NORMAL,     INPUT),
+
+       /* SDMMC */
+       DEFAULT_PINMUX(GMI_IORDY,       RSVD1,           PULL_UP,   NORMAL,     INPUT),
+
+       /* CODEC */
+       DEFAULT_PINMUX(SPI2_SCK,        SPI2,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(SPI2_CS1_N,      SPI2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_CS2_N,       RSVD1,           NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(GMI_CS3_N,       RSVD1,           NORMAL,    NORMAL,     INPUT),
+
+       /* OTHERS */
+       DEFAULT_PINMUX(KB_ROW3,         KBC,             NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_DQS,         RSVD1,           NORMAL,    NORMAL,     INPUT),
+
+       DEFAULT_PINMUX(GMI_AD15,        RSVD1,           PULL_UP,   NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(GMI_CLK,         RSVD1,           PULL_UP,   NORMAL,     INPUT),
+
+       DEFAULT_PINMUX(GMI_RST_N,       NAND,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(LCD_DC0,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_CS0_N,       DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_CS1_N,       DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_SCK,         DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(LCD_SDIN,        DISPLAYA,        NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(CRT_HSYNC,       CRT,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(CRT_VSYNC,       CRT,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(PEX_WAKE_N,      PCIE,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(PEX_L2_PRSNT_N,  PCIE,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(PEX_L2_RST_N,    PCIE,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE,            NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(HDMI_CEC,        CEC,             NORMAL,    NORMAL,     INPUT),
+
+       DEFAULT_PINMUX(KB_ROW15,        KBC,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(SPI2_CS2_N,      SPI2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI2_MISO,       SPI2,            NORMAL,    NORMAL,     INPUT),
+       DEFAULT_PINMUX(SPI2_MOSI,       SPI2,            NORMAL,    NORMAL,     INPUT),
+
+       DEFAULT_PINMUX(KB_ROW11,        KBC,             NORMAL,    NORMAL,     OUTPUT),
+       DEFAULT_PINMUX(KB_ROW12,        KBC,             NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(KB_ROW13,        KBC,             NORMAL,    TRISTATE,   OUTPUT),
+};
+
+/*Do not use for now*/
+static __initdata struct tegra_pingroup_config unused_pins_lowpower[] = {
+       DEFAULT_PINMUX(ULPI_CLK,        ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA0,      ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA1,      ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA2,      ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA3,      ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA4,      ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA5,      ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA6,      ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA7,      ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_DIR,        ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_NXT,        ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(ULPI_STP,        ULPI,          NORMAL,    TRISTATE,   OUTPUT),
+
+       DEFAULT_PINMUX(GMI_AD10,        PWM2,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_AD12,        RSVD1,         NORMAL,    TRISTATE,   INPUT),
+       DEFAULT_PINMUX(GMI_AD13,        RSVD1,         NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(CLK1_REQ,        DAP,           NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_ADV_N,       RSVD1,         NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_CS0_N,       RSVD1,         NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_CS1_N,       RSVD1,         NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_CS4_N,       RSVD1,         NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_CS6_N,       NAND,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_CS7_N,       NAND,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_OE_N,        RSVD1,         NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GMI_WR_N,        RSVD1,         NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(PEX_L0_PRSNT_N,  PCIE,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(PEX_L0_RST_N,    PCIE,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(PEX_L1_PRSNT_N,  PCIE,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(PEX_L1_RST_N,    PCIE,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GPIO_PV2,        OWR,           NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(GPIO_PV3,        RSVD1,         NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(HDMI_CEC,        CEC,           NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(KB_COL4,         KBC,           NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(KB_COL5,         KBC,           NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(KB_COL6,         KBC,           NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(KB_COL7,         KBC,           NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(CLK3_REQ,        DEV3,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D0,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D1,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D10,          VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D11,          VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D2,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D3,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D4,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D5,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D6,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D7,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D8,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_D9,           VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_HSYNC,        VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_MCLK,         VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_PCLK,         VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(VI_VSYNC,        VI,            NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(DAP3_DIN,        I2S2,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(DAP3_DOUT,       I2S2,          NORMAL,    TRISTATE,   OUTPUT),
+       DEFAULT_PINMUX(DAP3_SCLK,       I2S2,          NORMAL,    TRISTATE,   OUTPUT),
+
+};
+
+/* We are disabling this code for now. */
+#define GPIO_INIT_PIN_MODE(_gpio, _is_input, _value)   \
+       {                                       \
+               .gpio_nr        = _gpio,        \
+               .is_input       = _is_input,    \
+               .value          = _value,       \
+       }
+
+static struct gpio_init_pin_info init_gpio_mode_kai_common[] = {
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PDD7, false, 0),
+       GPIO_INIT_PIN_MODE(TEGRA_GPIO_PCC6, false, 0),
+};
+
+static void __init kai_gpio_init_configure(void)
+{
+       int len;
+       int i;
+       struct gpio_init_pin_info *pins_info;
+
+       len = ARRAY_SIZE(init_gpio_mode_kai_common);
+       pins_info = init_gpio_mode_kai_common;
+
+       for (i = 0; i < len; ++i) {
+               tegra_gpio_init_configure(pins_info->gpio_nr,
+                       pins_info->is_input, pins_info->value);
+               pins_info++;
+       }
+}
+
+int __init kai_pinmux_init(void)
+{
+       kai_gpio_init_configure();
+
+       tegra_pinmux_config_table(kai_pinmux_common, ARRAY_SIZE(kai_pinmux_common));
+       tegra_drive_pinmux_config_table(kai_drive_pinmux,
+                                       ARRAY_SIZE(kai_drive_pinmux));
+
+       tegra_pinmux_config_table(unused_pins_lowpower,
+               ARRAY_SIZE(unused_pins_lowpower));
+
+       return 0;
+}
+
+#define PIN_GPIO_LPM(_name, _gpio, _is_input, _value)  \
+       {                                       \
+               .name           = _name,        \
+               .gpio_nr        = _gpio,        \
+               .is_gpio        = true,         \
+               .is_input       = _is_input,    \
+               .value          = _value,       \
+       }
+
+struct gpio_init_pin_info pin_lpm_kai_common[] = {
+       PIN_GPIO_LPM("GMI_CS4_N", TEGRA_GPIO_PK2, 1, 0),
+       PIN_GPIO_LPM("GMI_CS7",   TEGRA_GPIO_PI6, 1, 0),
+       PIN_GPIO_LPM("GMI_CS0",   TEGRA_GPIO_PJ0, 1, 0),
+       PIN_GPIO_LPM("GMI_CS1",   TEGRA_GPIO_PJ2, 1, 0),
+};
+
+static void set_unused_pin_gpio(struct gpio_init_pin_info *lpm_pin_info,
+               int list_count)
+{
+       int i;
+       struct gpio_init_pin_info *pin_info;
+       int ret;
+
+       for (i = 0; i < list_count; ++i) {
+               pin_info = (struct gpio_init_pin_info *)(lpm_pin_info + i);
+               if (!pin_info->is_gpio)
+                       continue;
+
+               ret = gpio_request(pin_info->gpio_nr, pin_info->name);
+               if (ret < 0) {
+                       pr_err("%s() Error in gpio_request() for gpio %d\n",
+                                       __func__, pin_info->gpio_nr);
+                       continue;
+               }
+               if (pin_info->is_input)
+                       ret = gpio_direction_input(pin_info->gpio_nr);
+               else
+                       ret = gpio_direction_output(pin_info->gpio_nr,
+                                                       pin_info->value);
+               if (ret < 0) {
+                       pr_err("%s() Error in setting gpio %d to in/out\n",
+                               __func__, pin_info->gpio_nr);
+                       gpio_free(pin_info->gpio_nr);
+                       continue;
+               }
+               tegra_gpio_enable(pin_info->gpio_nr);
+       }
+}
+
+/* Initialize the pins to desired state as per power/asic/system-eng
+ * recomendation */
+int __init kai_pins_state_init(void)
+{
+       set_unused_pin_gpio(&pin_lpm_kai_common[0],
+                           ARRAY_SIZE(pin_lpm_kai_common));
+
+       return 0;
+}
diff --git a/arch/arm/mach-tegra/board-kai-power.c b/arch/arm/mach-tegra/board-kai-power.c
new file mode 100644 (file)
index 0000000..6a65d0e
--- /dev/null
@@ -0,0 +1,607 @@
+/*
+ * arch/arm/mach-tegra/board-kai-power.c
+ *
+ * Copyright (C) 2012 NVIDIA, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+#include <linux/i2c.h>
+#include <linux/pda_power.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <linux/regulator/machine.h>
+#include <linux/mfd/max77663-core.h>
+#include <linux/regulator/max77663-regulator.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/regulator/gpio-switch-regulator.h>
+#include <linux/power/gpio-charger.h>
+
+#include <asm/mach-types.h>
+
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/pinmux.h>
+#include <mach/edp.h>
+
+#include "gpio-names.h"
+#include "board.h"
+#include "board-kai.h"
+#include "pm.h"
+#include "wakeups-t3.h"
+#include "tegra3_tsensor.h"
+
+#define PMC_CTRL               0x0
+#define PMC_CTRL_INTR_LOW      (1 << 17)
+
+static struct regulator_consumer_supply max77663_sd0_supply[] = {
+       REGULATOR_SUPPLY("vdd_cpu", NULL),
+};
+
+static struct regulator_consumer_supply max77663_sd1_supply[] = {
+       REGULATOR_SUPPLY("vdd_core", NULL),
+};
+
+static struct regulator_consumer_supply max77663_sd2_supply[] = {
+       REGULATOR_SUPPLY("vdd_gen1v8", NULL),
+       REGULATOR_SUPPLY("avdd_hdmi_pll", NULL),
+       REGULATOR_SUPPLY("avdd_usb_pll", NULL),
+       REGULATOR_SUPPLY("avdd_osc", NULL),
+       REGULATOR_SUPPLY("vddio_sys", NULL),
+       REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"),
+       REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL),
+       REGULATOR_SUPPLY("vddio_uart", NULL),
+       REGULATOR_SUPPLY("pwrdet_uart", NULL),
+       REGULATOR_SUPPLY("vddio_bb", NULL),
+       REGULATOR_SUPPLY("pwrdet_bb", NULL),
+       REGULATOR_SUPPLY("vddio_lcd_pmu", NULL),
+       REGULATOR_SUPPLY("pwrdet_lcd", NULL),
+       REGULATOR_SUPPLY("vddio_audio", NULL),
+       REGULATOR_SUPPLY("pwrdet_audio", NULL),
+       REGULATOR_SUPPLY("vddio_cam", NULL),
+       REGULATOR_SUPPLY("pwrdet_cam", NULL),
+       REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"),
+       REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL),
+       REGULATOR_SUPPLY("vddio_vi", NULL),
+       REGULATOR_SUPPLY("pwrdet_vi", NULL),
+       REGULATOR_SUPPLY("vcore_nand", NULL),
+       REGULATOR_SUPPLY("pwrdet_nand", NULL),
+};
+
+static struct regulator_consumer_supply max77663_sd3_supply[] = {
+       REGULATOR_SUPPLY("vdd_ddr3l_1v35", NULL),
+};
+
+static struct regulator_consumer_supply max77663_ldo0_supply[] = {
+       REGULATOR_SUPPLY("vdd_ddr_hs", NULL),
+};
+
+static struct regulator_consumer_supply max77663_ldo1_supply[] = {
+};
+
+static struct regulator_consumer_supply max77663_ldo2_supply[] = {
+       REGULATOR_SUPPLY("vdd_ddr_rx", NULL),
+};
+
+static struct regulator_consumer_supply max77663_ldo3_supply[] = {
+       REGULATOR_SUPPLY("vmmc", NULL),
+};
+
+static struct regulator_consumer_supply max77663_ldo4_supply[] = {
+       REGULATOR_SUPPLY("vdd_rtc", NULL),
+};
+
+static struct regulator_consumer_supply max77663_ldo5_supply[] = {
+       REGULATOR_SUPPLY("vdd_sensor_2v8", NULL),
+};
+
+static struct regulator_consumer_supply max77663_ldo6_supply[] = {
+       REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"),
+       REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL),
+};
+
+static struct regulator_consumer_supply max77663_ldo7_supply[] = {
+       REGULATOR_SUPPLY("avdd_dsi_csi", NULL),
+       REGULATOR_SUPPLY("pwrdet_mipi", NULL),
+};
+
+static struct regulator_consumer_supply max77663_ldo8_supply[] = {
+       REGULATOR_SUPPLY("avdd_plla_p_c_s", NULL),
+       REGULATOR_SUPPLY("avdd_pllm", NULL),
+       REGULATOR_SUPPLY("avdd_pllu_d", NULL),
+       REGULATOR_SUPPLY("avdd_pllu_d2", NULL),
+       REGULATOR_SUPPLY("avdd_pllx", NULL),
+};
+
+static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = {
+       {
+               .src = FPS_SRC_0,
+               .en_src = FPS_EN_SRC_EN0,
+               .time_period = FPS_TIME_PERIOD_DEF,
+       },
+       {
+               .src = FPS_SRC_1,
+               .en_src = FPS_EN_SRC_EN1,
+               .time_period = FPS_TIME_PERIOD_DEF,
+       },
+       {
+               .src = FPS_SRC_2,
+               .en_src = FPS_EN_SRC_EN0,
+               .time_period = FPS_TIME_PERIOD_DEF,
+       },
+};
+
+#define MAX77663_PDATA_INIT(_id, _min_uV, _max_uV, _supply_reg,                \
+                           _always_on, _boot_on, _apply_uV,            \
+                           _init_apply, _init_enable, _init_uV,        \
+                           _fps_src, _fps_pu_period, _fps_pd_period, _flags) \
+       static struct max77663_regulator_platform_data max77663_regulator_pdata_##_id = \
+       {                                                               \
+               .init_data = {                                          \
+                       .constraints = {                                \
+                               .min_uV = _min_uV,                      \
+                               .max_uV = _max_uV,                      \
+                               .valid_modes_mask = (REGULATOR_MODE_NORMAL |  \
+                                                    REGULATOR_MODE_STANDBY), \
+                               .valid_ops_mask = (REGULATOR_CHANGE_MODE |    \
+                                                  REGULATOR_CHANGE_STATUS |  \
+                                                  REGULATOR_CHANGE_VOLTAGE), \
+                               .always_on = _always_on,                \
+                               .boot_on = _boot_on,                    \
+                               .apply_uV = _apply_uV,                  \
+                       },                                              \
+                       .num_consumer_supplies =                        \
+                               ARRAY_SIZE(max77663_##_id##_supply),    \
+                       .consumer_supplies = max77663_##_id##_supply,   \
+                       .supply_regulator = _supply_reg,                \
+               },                                                      \
+               .init_apply = _init_apply,                              \
+               .init_enable = _init_enable,                            \
+               .init_uV = _init_uV,                                    \
+               .fps_src = _fps_src,                                    \
+               .fps_pu_period = _fps_pu_period,                        \
+               .fps_pd_period = _fps_pd_period,                        \
+               .fps_cfgs = max77663_fps_cfgs,                          \
+               .flags = _flags,                                        \
+       }
+
+MAX77663_PDATA_INIT(sd0,  600000, 3387500, NULL, 1, 0, 0,
+                   0, 0, -1, FPS_SRC_NONE, -1, -1, EN2_CTRL_SD0 | SD_FSRADE_DISABLE);
+
+MAX77663_PDATA_INIT(sd1,  800000, 1587500, NULL, 1, 0, 0,
+                   1, 1, -1, FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE);
+
+MAX77663_PDATA_INIT(sd2,  600000, 3387500, NULL, 1, 0, 0,
+                   1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
+
+MAX77663_PDATA_INIT(sd3,  600000, 3387500, NULL, 1, 0, 0,
+                   1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
+
+MAX77663_PDATA_INIT(ldo0, 800000, 2350000, max77663_rails(sd3), 1, 0, 0,
+                   1, 1, -1, FPS_SRC_1, -1, -1, 0);
+
+MAX77663_PDATA_INIT(ldo1, 800000, 2350000, max77663_rails(sd3), 0, 0, 0,
+                   0, 0, -1, FPS_SRC_NONE, -1, -1, 0);
+
+MAX77663_PDATA_INIT(ldo2, 800000, 3950000, NULL, 1, 0, 0,
+                   1, 1, -1, FPS_SRC_1, -1, -1, 0);
+
+MAX77663_PDATA_INIT(ldo3, 800000, 3950000, NULL, 1, 0, 0,
+                   1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
+
+MAX77663_PDATA_INIT(ldo4, 800000, 1587500, NULL, 0, 0, 0,
+                   1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
+
+MAX77663_PDATA_INIT(ldo5, 800000, 2800000, NULL, 0, 0, 0,
+                   1, 1, -1, FPS_SRC_NONE, -1, -1, 0);
+
+MAX77663_PDATA_INIT(ldo6, 800000, 3950000, NULL, 0, 0, 0,
+                   0, 0, -1, FPS_SRC_NONE, -1, -1, 0);
+
+MAX77663_PDATA_INIT(ldo7, 800000, 3950000, max77663_rails(sd3), 0, 0, 0,
+                   0, 0, -1, FPS_SRC_NONE, -1, -1, 0);
+
+MAX77663_PDATA_INIT(ldo8, 800000, 3950000, max77663_rails(sd3), 0, 0, 0,
+                   1, 1, -1, FPS_SRC_1, -1, -1, 0);
+
+#define MAX77663_REG(_id, _data)                                       \
+       {                                                               \
+               .name = "max77663-regulator",                           \
+               .id = MAX77663_REGULATOR_ID_##_id,                      \
+               .platform_data = &max77663_regulator_pdata_##_data,             \
+       }
+
+#define MAX77663_RTC()                                                 \
+       {                                                               \
+               .name = "max77663-rtc",                                 \
+               .id = 0,                                                \
+       }
+
+static struct mfd_cell max77663_subdevs[] = {
+       MAX77663_REG(SD0, sd0),
+       MAX77663_REG(SD1, sd1),
+       MAX77663_REG(SD2, sd2),
+       MAX77663_REG(SD3, sd3),
+       MAX77663_REG(LDO0, ldo0),
+       MAX77663_REG(LDO1, ldo1),
+       MAX77663_REG(LDO2, ldo2),
+       MAX77663_REG(LDO3, ldo3),
+       MAX77663_REG(LDO4, ldo4),
+       MAX77663_REG(LDO5, ldo5),
+       MAX77663_REG(LDO6, ldo6),
+       MAX77663_REG(LDO7, ldo7),
+       MAX77663_REG(LDO8, ldo8),
+       MAX77663_RTC(),
+};
+
+static struct max77663_gpio_config max77663_gpio_cfgs[] = {
+       {
+               .gpio = MAX77663_GPIO0,
+               .dir = GPIO_DIR_OUT,
+               .dout = GPIO_DOUT_LOW,
+               .out_drv = GPIO_OUT_DRV_PUSH_PULL,
+               .alternate = GPIO_ALT_DISABLE,
+       },
+       {
+               .gpio = MAX77663_GPIO1,
+               .dir = GPIO_DIR_OUT,
+               .dout = GPIO_DOUT_LOW,
+               .out_drv = GPIO_OUT_DRV_PUSH_PULL,
+               .alternate = GPIO_ALT_DISABLE,
+       },
+       {
+               .gpio = MAX77663_GPIO2,
+               .dir = GPIO_DIR_OUT,
+               .dout = GPIO_DOUT_HIGH,
+               .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
+               .alternate = GPIO_ALT_DISABLE,
+       },
+       {
+               .gpio = MAX77663_GPIO3,
+               .dir = GPIO_DIR_OUT,
+               .dout = GPIO_DOUT_HIGH,
+               .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
+               .alternate = GPIO_ALT_DISABLE,
+       },
+       {
+               .gpio = MAX77663_GPIO4,
+               .dir = GPIO_DIR_OUT,
+               .dout = GPIO_DOUT_HIGH,
+               .out_drv = GPIO_OUT_DRV_OPEN_DRAIN,
+               .alternate = GPIO_ALT_ENABLE,
+       },
+       {
+               .gpio = MAX77663_GPIO5,
+               .dir = GPIO_DIR_OUT,
+               .dout = GPIO_DOUT_LOW,
+               .out_drv = GPIO_OUT_DRV_PUSH_PULL,
+               .alternate = GPIO_ALT_DISABLE,
+       },
+       {
+               .gpio = MAX77663_GPIO6,
+               .dir = GPIO_DIR_IN,
+               .alternate = GPIO_ALT_DISABLE,
+       },
+       {
+               .gpio = MAX77663_GPIO7,
+               .dir = GPIO_DIR_OUT,
+               .dout = GPIO_DOUT_LOW,
+               .out_drv = GPIO_OUT_DRV_PUSH_PULL,
+               .alternate = GPIO_ALT_DISABLE,
+       },
+};
+
+static struct max77663_platform_data max7763_pdata = {
+       .irq_base       = MAX77663_IRQ_BASE,
+       .gpio_base      = MAX77663_GPIO_BASE,
+
+       .num_gpio_cfgs  = ARRAY_SIZE(max77663_gpio_cfgs),
+       .gpio_cfgs      = max77663_gpio_cfgs,
+
+       .num_subdevs    = ARRAY_SIZE(max77663_subdevs),
+       .sub_devices    = max77663_subdevs,
+};
+
+static struct i2c_board_info __initdata max77663_regulators[] = {
+       {
+               /* The I2C address was determined by OTP factory setting */
+               I2C_BOARD_INFO("max77663", 0x3c),
+               .irq            = INT_EXTERNAL_PMU,
+               .platform_data  = &max7763_pdata,
+       },
+};
+
+static int __init kai_max77663_regulator_init(void)
+{
+       void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+       u32 pmc_ctrl;
+
+       /* configure the power management controller to trigger PMU
+        * interrupts when low */
+       pmc_ctrl = readl(pmc + PMC_CTRL);
+       writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
+
+       i2c_register_board_info(4, max77663_regulators,
+                               ARRAY_SIZE(max77663_regulators));
+
+       return 0;
+}
+
+static struct regulator_consumer_supply gpio_switch_en_3v3_sys_supply[] = {
+       REGULATOR_SUPPLY("vdd_3v3", NULL),
+       REGULATOR_SUPPLY("vdd_3v3_devices", NULL),
+       REGULATOR_SUPPLY("debug_cons", NULL),
+       REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL),
+};
+static int gpio_switch_en_3v3_sys_voltages[] = { 3300};
+
+static struct regulator_consumer_supply gpio_switch_en_avdd_hdmi_usb_supply[] = {
+       REGULATOR_SUPPLY("avdd_hdmi", NULL),
+       REGULATOR_SUPPLY("avdd_usb", NULL),
+       REGULATOR_SUPPLY("vddio_gmi", NULL),
+};
+static int gpio_switch_en_avdd_hdmi_usb_voltages[] = { 3300};
+
+static struct regulator_consumer_supply gpio_switch_en_1v8_cam_supply[] = {
+       REGULATOR_SUPPLY("vdd_1v8_cam1", NULL),
+       REGULATOR_SUPPLY("vdd_1v8_cam2", NULL),
+       REGULATOR_SUPPLY("vdd_1v8_cam3", NULL),
+};
+static int gpio_switch_en_1v8_cam_voltages[] = { 1800};
+
+static struct regulator_consumer_supply gpio_switch_en_vddio_vid_supply[] = {
+       REGULATOR_SUPPLY("vdd_hdmi_con", NULL),
+};
+static int gpio_switch_en_vddio_vid_voltages[] = { 5000};
+
+static struct regulator_consumer_supply gpio_switch_en_3v3_modem_supply[] = {
+       REGULATOR_SUPPLY("vdd_mini_card", NULL),
+};
+static int gpio_switch_en_3v3_modem_voltages[] = { 3300};
+
+static struct regulator_consumer_supply gpio_switch_en_vdd_pnl_supply[] = {
+       REGULATOR_SUPPLY("vdd_lvds", NULL),
+       REGULATOR_SUPPLY("vdd_lcd_panel", NULL),
+       REGULATOR_SUPPLY("vdd_touch", NULL),
+       REGULATOR_SUPPLY("vddio_ts", NULL),
+};
+static int gpio_switch_en_vdd_pnl_voltages[] = { 3300};
+
+static struct regulator_consumer_supply gpio_switch_en_cam3_ldo_supply[] = {
+       REGULATOR_SUPPLY("vdd_cam3", NULL),
+};
+static int gpio_switch_en_cam3_ldo_voltages[] = { 3300};
+
+static struct regulator_consumer_supply gpio_switch_en_vdd_com_supply[] = {
+       REGULATOR_SUPPLY("vdd_com_bd", NULL),
+};
+static int gpio_switch_en_vdd_com_voltages[] = { 3300};
+
+static struct regulator_consumer_supply gpio_switch_en_vdd_sdmmc1_supply[] = {
+       REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.0"),
+};
+static int gpio_switch_en_vdd_sdmmc1_voltages[] = { 3300};
+
+static struct regulator_consumer_supply gpio_switch_en_3v3_fuse_supply[] = {
+       REGULATOR_SUPPLY("vpp_fuse", NULL),
+};
+static int gpio_switch_en_3v3_fuse_voltages[] = { 3300};
+
+static struct regulator_consumer_supply gpio_switch_cdc_en_supply[] = {
+       REGULATOR_SUPPLY("cdc_en", NULL),
+};
+static int gpio_switch_cdc_en_voltages[] = { 1200};
+
+/* Macro for defining gpio switch regulator sub device data */
+#define GREG_INIT(_id, _var, _name, _input_supply, _always_on, _boot_on, \
+       _gpio_nr, _active_low, _init_state, _pg, _enable, _disable)      \
+       static struct gpio_switch_regulator_subdev_data gpio_pdata_##_var =  \
+       {                                                               \
+               .regulator_name = "gpio-switch-"#_name,                 \
+               .input_supply   = _input_supply,                        \
+               .id             = _id,                                  \
+               .gpio_nr        = _gpio_nr,                             \
+               .pin_group      = _pg,                                  \
+               .active_low     = _active_low,                          \
+               .init_state     = _init_state,                          \
+               .voltages       = gpio_switch_##_name##_voltages,       \
+               .n_voltages     = ARRAY_SIZE(gpio_switch_##_name##_voltages), \
+               .num_consumer_supplies =                                \
+                               ARRAY_SIZE(gpio_switch_##_name##_supply), \
+               .consumer_supplies = gpio_switch_##_name##_supply,      \
+               .constraints = {                                        \
+                       .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
+                                            REGULATOR_MODE_STANDBY),   \
+                       .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
+                                          REGULATOR_CHANGE_STATUS |    \
+                                          REGULATOR_CHANGE_VOLTAGE),   \
+                       .always_on = _always_on,                        \
+                       .boot_on = _boot_on,                            \
+               },                                                      \
+               .enable_rail = _enable,                                 \
+               .disable_rail = _disable,                               \
+       }
+
+GREG_INIT(1, en_3v3_sys,       en_3v3_sys,             NULL,
+       1,      0,      MAX77663_GPIO_BASE + MAX77663_GPIO3,    false,  1,      0,      0,      0);
+GREG_INIT(2, en_avdd_hdmi_usb, en_avdd_hdmi_usb,       "vdd_3v3_devices",
+       1,      0,      MAX77663_GPIO_BASE + MAX77663_GPIO2,    false,  1,      0,      0,      0);
+GREG_INIT(3, en_1v8_cam,       en_1v8_cam,             "vdd_gen1v8",
+       0,      0,      TEGRA_GPIO_PS0,                         false,  0,      0,      0,      0);
+GREG_INIT(4, en_vddio_vid_oc,  en_vddio_vid,           NULL,
+       0,      0,      TEGRA_GPIO_PB2,                         false,  0,      0,      0,      0);
+GREG_INIT(5, en_3v3_modem,     en_3v3_modem,           NULL,
+       0,      0,      TEGRA_GPIO_PP0,                         false,  0,      0,      0,      0);
+GREG_INIT(6, en_vdd_pnl,       en_vdd_pnl,             "vdd_3v3_devices",
+       0,      0,      TEGRA_GPIO_PW1,                         false,  0,      0,      0,      0);
+GREG_INIT(7, en_cam3_ldo,      en_cam3_ldo,            "vdd_3v3_devices",
+       0,      0,      TEGRA_GPIO_PR7,                         false,  0,      0,      0,      0);
+GREG_INIT(8, en_vdd_com,       en_vdd_com,             "vdd_3v3_devices",
+       0,      0,      TEGRA_GPIO_PD0,                         false,  0,      0,      0,      0);
+GREG_INIT(9,  en_vdd_sdmmc1,   en_vdd_sdmmc1,          "vdd_3v3_devices",
+       0,      0,      TEGRA_GPIO_PC6,                         false,  0,      0,      0,      0);
+GREG_INIT(10, en_3v3_fuse,     en_3v3_fuse,            "vdd_3v3_devices",
+       0,      0,      TEGRA_GPIO_PC1,                         false,  0,      0,      0,      0);
+GREG_INIT(11, cdc_en,          cdc_en,                 "vddio_audio",
+       0,      1,      TEGRA_GPIO_PX2,                         false,  0,      0,      0,      0);
+
+
+#define ADD_GPIO_REG(_name) &gpio_pdata_##_name
+
+#define E1565_GPIO_REG \
+       ADD_GPIO_REG(en_3v3_sys),               \
+       ADD_GPIO_REG(en_avdd_hdmi_usb),         \
+       ADD_GPIO_REG(en_1v8_cam),               \
+       ADD_GPIO_REG(en_vddio_vid_oc),          \
+       ADD_GPIO_REG(en_3v3_modem),             \
+       ADD_GPIO_REG(en_vdd_pnl),               \
+       ADD_GPIO_REG(en_cam3_ldo),              \
+       ADD_GPIO_REG(en_vdd_com),               \
+       ADD_GPIO_REG(en_vdd_sdmmc1),            \
+       ADD_GPIO_REG(en_3v3_fuse),              \
+       ADD_GPIO_REG(cdc_en),                   \
+
+
+static struct gpio_switch_regulator_subdev_data *gswitch_subdevs[] = {
+       E1565_GPIO_REG
+};
+
+static struct gpio_switch_regulator_platform_data gswitch_pdata = {
+       .subdevs = gswitch_subdevs,
+       .num_subdevs = ARRAY_SIZE(gswitch_subdevs),
+};
+
+static struct platform_device gswitch_regulator_pdata = {
+       .name = "gpio-switch-regulator",
+       .id   = -1,
+       .dev  = {
+            .platform_data = &gswitch_pdata,
+       },
+};
+
+static int __init kai_max77663_gpio_switch_regulator_init(void)
+{
+       int i;
+
+       for (i = 0; i < gswitch_pdata.num_subdevs; ++i) {
+               struct gpio_switch_regulator_subdev_data *gswitch_data =
+                                               gswitch_pdata.subdevs[i];
+               if (gswitch_data->gpio_nr <= TEGRA_NR_GPIOS)
+                       tegra_gpio_enable(gswitch_data->gpio_nr);
+       }
+
+       return platform_device_register(&gswitch_regulator_pdata);
+}
+
+int __init kai_regulator_init(void)
+{
+       void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+       u32 pmc_ctrl;
+       int ret;
+
+       /* configure the power management controller to trigger PMU
+        * interrupts when low */
+
+       pmc_ctrl = readl(pmc + PMC_CTRL);
+       writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
+
+       ret = kai_max77663_regulator_init();
+       if (ret < 0)
+               return ret;
+
+       return kai_max77663_gpio_switch_regulator_init();
+}
+
+static void kai_board_suspend(int lp_state, enum suspend_stage stg)
+{
+       if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_SUSPEND_BEFORE_CPU))
+               tegra_console_uart_suspend();
+}
+
+static void kai_board_resume(int lp_state, enum resume_stage stg)
+{
+       if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_RESUME_AFTER_CPU))
+               tegra_console_uart_resume();
+}
+
+static struct tegra_suspend_platform_data kai_suspend_data = {
+       .cpu_timer      = 2000,
+       .cpu_off_timer  = 200,
+       .suspend_mode   = TEGRA_SUSPEND_LP0,
+       .core_timer     = 0x7e7e,
+       .core_off_timer = 0,
+       .corereq_high   = true,
+       .sysclkreq_high = true,
+       .cpu_lp2_min_residency = 2000,
+       .board_suspend = kai_board_suspend,
+       .board_resume = kai_board_resume,
+};
+
+int __init kai_suspend_init(void)
+{
+       tegra_init_suspend(&kai_suspend_data);
+       return 0;
+}
+
+static void kai_power_off(void)
+{
+       int ret;
+       pr_err("kai: Powering off the device\n");
+       ret = max77663_power_off();
+       if (ret)
+               pr_err("kai: failed to power off\n");
+
+       while (1)
+               ;
+}
+
+int __init kai_power_off_init(void)
+{
+       pm_power_off = kai_power_off;
+
+       return 0;
+}
+
+static struct tegra_tsensor_pmu_data  tpdata = {
+       .poweroff_reg_addr = 0x3F,
+       .poweroff_reg_data = 0x80,
+       .reset_tegra = 1,
+       .controller_type = 0,
+       .i2c_controller_id = 4,
+       .pinmux = 0,
+       .pmu_16bit_ops = 0,
+       .pmu_i2c_addr = 0x2D,
+};
+
+void __init kai_tsensor_init(void)
+{
+       tegra3_tsensor_init(&tpdata);
+}
+
+#ifdef CONFIG_TEGRA_EDP_LIMITS
+
+int __init kai_edp_init(void)
+{
+       unsigned int regulator_mA;
+
+       regulator_mA = get_maximum_cpu_current_supported();
+       if (!regulator_mA)
+               regulator_mA = 6000; /* regular T30/s */
+       pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
+
+       tegra_init_cpu_edp_limits(regulator_mA);
+       return 0;
+}
+#endif
diff --git a/arch/arm/mach-tegra/board-kai-sdhci.c b/arch/arm/mach-tegra/board-kai-sdhci.c
new file mode 100644 (file)
index 0000000..99f7736
--- /dev/null
@@ -0,0 +1,163 @@
+/*
+ * arch/arm/mach-tegra/board-kai-sdhci.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2012 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/resource.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/mmc/host.h>
+
+#include <asm/mach-types.h>
+#include <mach/irqs.h>
+#include <mach/iomap.h>
+#include <mach/sdhci.h>
+
+#include "gpio-names.h"
+#include "board.h"
+#include "board-kai.h"
+
+#define KAI_SD_CD      TEGRA_GPIO_PI5
+
+static struct resource sdhci_resource0[] = {
+       [0] = {
+               .start  = INT_SDMMC1,
+               .end    = INT_SDMMC1,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [1] = {
+               .start  = TEGRA_SDMMC1_BASE,
+               .end    = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct resource sdhci_resource2[] = {
+       [0] = {
+               .start  = INT_SDMMC3,
+               .end    = INT_SDMMC3,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [1] = {
+               .start  = TEGRA_SDMMC3_BASE,
+               .end    = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct resource sdhci_resource3[] = {
+       [0] = {
+               .start  = INT_SDMMC4,
+               .end    = INT_SDMMC4,
+               .flags  = IORESOURCE_IRQ,
+       },
+       [1] = {
+               .start  = TEGRA_SDMMC4_BASE,
+               .end    = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
+               .flags  = IORESOURCE_MEM,
+       },
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
+       .mmc_data = {
+               .built_in = 1,
+       },
+       .cd_gpio = -1,
+       .wp_gpio = -1,
+       .power_gpio = -1,
+/*     .tap_delay = 6,
+       .is_voltage_switch_supported = false,
+       .vdd_rail_name = NULL,
+       .slot_rail_name = NULL,
+       .vdd_max_uv = -1,
+       .vdd_min_uv = -1,
+       .max_clk = 0,
+       .is_8bit_supported = false, */
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
+       .cd_gpio = KAI_SD_CD,
+       .wp_gpio = -1,
+       .power_gpio = -1,
+/*     .tap_delay = 6,
+       .is_voltage_switch_supported = true,
+       .vdd_rail_name = "vddio_sdmmc1",
+       .slot_rail_name = "vddio_sd_slot",
+       .vdd_max_uv = 3320000,
+       .vdd_min_uv = 3280000,
+       .max_clk = 208000000,
+       .is_8bit_supported = false, */
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
+       .cd_gpio = -1,
+       .wp_gpio = -1,
+       .power_gpio = -1,
+       .is_8bit = 1,
+       .tap_delay = 0x0F,
+       .mmc_data = {
+               .built_in = 1,
+       }
+/*     .tap_delay = 6,
+       .is_voltage_switch_supported = false,
+       .vdd_rail_name = NULL,
+       .slot_rail_name = NULL,
+       .vdd_max_uv = -1,
+       .vdd_min_uv = -1,
+       .max_clk = 48000000,
+       .is_8bit_supported = true, */
+};
+
+static struct platform_device tegra_sdhci_device0 = {
+       .name           = "sdhci-tegra",
+       .id             = 0,
+       .resource       = sdhci_resource0,
+       .num_resources  = ARRAY_SIZE(sdhci_resource0),
+       .dev = {
+               .platform_data = &tegra_sdhci_platform_data0,
+       },
+};
+
+static struct platform_device tegra_sdhci_device2 = {
+       .name           = "sdhci-tegra",
+       .id             = 2,
+       .resource       = sdhci_resource2,
+       .num_resources  = ARRAY_SIZE(sdhci_resource2),
+       .dev = {
+               .platform_data = &tegra_sdhci_platform_data2,
+       },
+};
+
+static struct platform_device tegra_sdhci_device3 = {
+       .name           = "sdhci-tegra",
+       .id             = 3,
+       .resource       = sdhci_resource3,
+       .num_resources  = ARRAY_SIZE(sdhci_resource3),
+       .dev = {
+               .platform_data = &tegra_sdhci_platform_data3,
+       },
+};
+
+int __init kai_sdhci_init(void)
+{
+       platform_device_register(&tegra_sdhci_device3);
+       platform_device_register(&tegra_sdhci_device2);
+       platform_device_register(&tegra_sdhci_device0);
+
+       return 0;
+}
diff --git a/arch/arm/mach-tegra/board-kai.c b/arch/arm/mach-tegra/board-kai.c
new file mode 100644 (file)
index 0000000..408d0db
--- /dev/null
@@ -0,0 +1,600 @@
+/*
+ * arch/arm/mach-tegra/board-kai.c
+ *
+ * Copyright (c) 2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/serial_8250.h>
+#include <linux/i2c.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/i2c-tegra.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/platform_data/tegra_usb.h>
+#include <linux/spi/spi.h>
+#include <linux/tegra_uart.h>
+#include <linux/memblock.h>
+#include <linux/spi-tegra.h>
+
+#include <mach/clk.h>
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/pinmux.h>
+#include <mach/iomap.h>
+#include <mach/io.h>
+#include <mach/i2s.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/usb_phy.h>
+#include <mach/thermal.h>
+
+#include "board.h"
+#include "clock.h"
+#include "board-kai.h"
+#include "devices.h"
+#include "gpio-names.h"
+#include "fuse.h"
+#include "pm.h"
+#include "wdt-recovery.h"
+
+/* All units are in millicelsius */
+static struct tegra_thermal_data thermal_data = {
+       .temp_throttle = 85000,
+       .temp_shutdown = 90000,
+       .temp_offset = TDIODE_OFFSET, /* temps based on tdiode */
+#ifdef CONFIG_TEGRA_EDP_LIMITS
+       .edp_offset = TDIODE_OFFSET,  /* edp based on tdiode */
+       .hysteresis_edp = 3000,
+#endif
+#ifdef CONFIG_TEGRA_THERMAL_SYSFS
+       .tc1 = 0,
+       .tc2 = 1,
+       .passive_delay = 2000,
+#else
+       .hysteresis_throttle = 1000,
+#endif
+};
+
+/* !!!TODO: Change for kai (Taken from Ventana) */
+static struct tegra_utmip_config utmi_phy_config[] = {
+       [0] = {
+                       .hssync_start_delay = 0,
+                       .idle_wait_delay = 17,
+                       .elastic_limit = 16,
+                       .term_range_adj = 6,
+                       .xcvr_setup = 15,
+                       .xcvr_setup_offset = 0,
+                       .xcvr_use_fuses = 1,
+                       .xcvr_lsfslew = 2,
+                       .xcvr_lsrslew = 2,
+       },
+       [1] = {
+                       .hssync_start_delay = 0,
+                       .idle_wait_delay = 17,
+                       .elastic_limit = 16,
+                       .term_range_adj = 6,
+                       .xcvr_setup = 15,
+                       .xcvr_setup_offset = 0,
+                       .xcvr_use_fuses = 1,
+                       .xcvr_lsfslew = 2,
+                       .xcvr_lsrslew = 2,
+       },
+       [2] = {
+                       .hssync_start_delay = 0,
+                       .idle_wait_delay = 17,
+                       .elastic_limit = 16,
+                       .term_range_adj = 6,
+                       .xcvr_setup = 8,
+                       .xcvr_setup_offset = 0,
+                       .xcvr_use_fuses = 1,
+                       .xcvr_lsfslew = 2,
+                       .xcvr_lsrslew = 2,
+       },
+};
+
+static __initdata struct tegra_clk_init_table kai_clk_init_table[] = {
+       /* name         parent          rate            enabled */
+       { "pll_m",      NULL,           0,              false},
+       { "hda",        "pll_p",        108000000,      false},
+       { "hda2codec_2x", "pll_p",      48000000,       false},
+       { "pwm",        "pll_p",        3187500,        false},
+       { "blink",      "clk_32k",      32768,          true},
+       { "i2s1",       "pll_a_out0",   0,              false},
+       { "i2s3",       "pll_a_out0",   0,              false},
+       { "spdif_out",  "pll_a_out0",   0,              false},
+       { "d_audio",    "pll_a_out0",   0,              false},
+       { "dam0",       "pll_a_out0",   0,              false},
+       { "dam1",       "pll_a_out0",   0,              false},
+       { "dam2",       "pll_a_out0",   0,              false},
+       { "audio1",     "i2s1_sync",    0,              false},
+       { "audio3",     "i2s3_sync",    0,              false},
+       { "vi_sensor",  "pll_p",        150000000,      false},
+       { "i2c1",       "pll_p",        3200000,        false},
+       { "i2c2",       "pll_p",        3200000,        false},
+       { "i2c3",       "pll_p",        3200000,        false},
+       { "i2c4",       "pll_p",        3200000,        false},
+       { "i2c5",       "pll_p",        3200000,        false},
+       { NULL,         NULL,           0,              0},
+};
+
+static struct tegra_i2c_platform_data kai_i2c1_platform_data = {
+       .adapter_nr     = 0,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 100000, 0 },
+       .scl_gpio               = {TEGRA_GPIO_PC4, 0},
+       .sda_gpio               = {TEGRA_GPIO_PC5, 0},
+       .arb_recovery = arb_lost_recovery,
+};
+
+static struct tegra_i2c_platform_data kai_i2c2_platform_data = {
+       .adapter_nr     = 1,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 100000, 0 },
+       .is_clkon_always = true,
+       .scl_gpio               = {TEGRA_GPIO_PT5, 0},
+       .sda_gpio               = {TEGRA_GPIO_PT6, 0},
+       .arb_recovery = arb_lost_recovery,
+};
+
+static struct tegra_i2c_platform_data kai_i2c3_platform_data = {
+       .adapter_nr     = 2,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 100000, 0 },
+       .scl_gpio               = {TEGRA_GPIO_PBB1, 0},
+       .sda_gpio               = {TEGRA_GPIO_PBB2, 0},
+       .arb_recovery = arb_lost_recovery,
+};
+
+static struct tegra_i2c_platform_data kai_i2c4_platform_data = {
+       .adapter_nr     = 3,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 100000, 0 },
+       .scl_gpio               = {TEGRA_GPIO_PV4, 0},
+       .sda_gpio               = {TEGRA_GPIO_PV5, 0},
+       .arb_recovery = arb_lost_recovery,
+};
+
+static struct tegra_i2c_platform_data kai_i2c5_platform_data = {
+       .adapter_nr     = 4,
+       .bus_count      = 1,
+       .bus_clk_rate   = { 400000, 0 },
+       .scl_gpio               = {TEGRA_GPIO_PZ6, 0},
+       .sda_gpio               = {TEGRA_GPIO_PZ7, 0},
+       .arb_recovery = arb_lost_recovery,
+};
+
+static void kai_i2c_init(void)
+{
+       tegra_i2c_device1.dev.platform_data = &kai_i2c1_platform_data;
+       tegra_i2c_device2.dev.platform_data = &kai_i2c2_platform_data;
+       tegra_i2c_device3.dev.platform_data = &kai_i2c3_platform_data;
+       tegra_i2c_device4.dev.platform_data = &kai_i2c4_platform_data;
+       tegra_i2c_device5.dev.platform_data = &kai_i2c5_platform_data;
+
+       platform_device_register(&tegra_i2c_device5);
+       platform_device_register(&tegra_i2c_device4);
+       platform_device_register(&tegra_i2c_device3);
+       platform_device_register(&tegra_i2c_device2);
+       platform_device_register(&tegra_i2c_device1);
+}
+
+static struct platform_device *kai_uart_devices[] __initdata = {
+       &tegra_uarta_device,
+       &tegra_uartb_device,
+       &tegra_uartc_device,
+       &tegra_uartd_device,
+       &tegra_uarte_device,
+};
+static struct uart_clk_parent uart_parent_clk[] = {
+       [0] = {.name = "clk_m"},
+       [1] = {.name = "pll_p"},
+#ifndef CONFIG_TEGRA_PLLM_RESTRICTED
+       [2] = {.name = "pll_m"},
+#endif
+};
+
+static struct tegra_uart_platform_data kai_uart_pdata;
+static struct tegra_uart_platform_data kai_loopback_uart_pdata;
+
+static void __init uart_debug_init(void)
+{
+       int debug_port_id;
+
+       debug_port_id = get_tegra_uart_debug_port_id();
+       if (debug_port_id < 0)
+               debug_port_id = 3;
+
+       switch (debug_port_id) {
+       case 0:
+               /* UARTA is the debug port. */
+               pr_info("Selecting UARTA as the debug console\n");
+               kai_uart_devices[0] = &debug_uarta_device;
+               debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
+               debug_uart_port_base = ((struct plat_serial8250_port *)(
+                       debug_uarta_device.dev.platform_data))->mapbase;
+               break;
+
+       case 1:
+               /* UARTB is the debug port. */
+               pr_info("Selecting UARTB as the debug console\n");
+               kai_uart_devices[1] = &debug_uartb_device;
+               debug_uart_clk = clk_get_sys("serial8250.0", "uartb");
+               debug_uart_port_base = ((struct plat_serial8250_port *)(
+                       debug_uartb_device.dev.platform_data))->mapbase;
+               break;
+
+       case 2:
+               /* UARTC is the debug port. */
+               pr_info("Selecting UARTC as the debug console\n");
+               kai_uart_devices[2] = &debug_uartc_device;
+               debug_uart_clk = clk_get_sys("serial8250.0", "uartc");
+               debug_uart_port_base = ((struct plat_serial8250_port *)(
+                       debug_uartc_device.dev.platform_data))->mapbase;
+               break;
+
+       case 3:
+               /* UARTD is the debug port. */
+               pr_info("Selecting UARTD as the debug console\n");
+               kai_uart_devices[3] = &debug_uartd_device;
+               debug_uart_clk = clk_get_sys("serial8250.0", "uartd");
+               debug_uart_port_base = ((struct plat_serial8250_port *)(
+                       debug_uartd_device.dev.platform_data))->mapbase;
+               break;
+
+       case 4:
+               /* UARTE is the debug port. */
+               pr_info("Selecting UARTE as the debug console\n");
+               kai_uart_devices[4] = &debug_uarte_device;
+               debug_uart_clk = clk_get_sys("serial8250.0", "uarte");
+               debug_uart_port_base = ((struct plat_serial8250_port *)(
+                       debug_uarte_device.dev.platform_data))->mapbase;
+               break;
+
+       default:
+               pr_info("The debug console id %d is invalid, Assuming UARTA",
+                       debug_port_id);
+               kai_uart_devices[0] = &debug_uarta_device;
+               debug_uart_clk = clk_get_sys("serial8250.0", "uarta");
+               debug_uart_port_base = ((struct plat_serial8250_port *)(
+                       debug_uarta_device.dev.platform_data))->mapbase;
+               break;
+       }
+       return;
+}
+
+static void __init kai_uart_init(void)
+{
+       struct clk *c;
+       int i;
+
+       for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) {
+               c = tegra_get_clock_by_name(uart_parent_clk[i].name);
+               if (IS_ERR_OR_NULL(c)) {
+                       pr_err("Not able to get the clock for %s\n",
+                                               uart_parent_clk[i].name);
+                       continue;
+               }
+               uart_parent_clk[i].parent_clk = c;
+               uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
+       }
+       kai_uart_pdata.parent_clk_list = uart_parent_clk;
+       kai_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk);
+       kai_loopback_uart_pdata.parent_clk_list = uart_parent_clk;
+       kai_loopback_uart_pdata.parent_clk_count =
+                                               ARRAY_SIZE(uart_parent_clk);
+       kai_loopback_uart_pdata.is_loopback = true;
+       tegra_uarta_device.dev.platform_data = &kai_uart_pdata;
+       tegra_uartb_device.dev.platform_data = &kai_uart_pdata;
+       tegra_uartc_device.dev.platform_data = &kai_uart_pdata;
+       tegra_uartd_device.dev.platform_data = &kai_uart_pdata;
+       /* UARTE is used for loopback test purpose */
+       tegra_uarte_device.dev.platform_data = &kai_loopback_uart_pdata;
+
+       /* Register low speed only if it is selected */
+       if (!is_tegra_debug_uartport_hs()) {
+               uart_debug_init();
+               /* Clock enable for the debug channel */
+               if (!IS_ERR_OR_NULL(debug_uart_clk)) {
+                       pr_info("The debug console clock name is %s\n",
+                                               debug_uart_clk->name);
+                       c = tegra_get_clock_by_name("pll_p");
+                       if (IS_ERR_OR_NULL(c))
+                               pr_err("Not getting the parent clock pll_p\n");
+                       else
+                               clk_set_parent(debug_uart_clk, c);
+
+                       clk_enable(debug_uart_clk);
+                       clk_set_rate(debug_uart_clk, clk_get_rate(c));
+               } else {
+                       pr_err("Not getting the clock %s for debug console\n",
+                                       debug_uart_clk->name);
+               }
+       }
+
+       platform_add_devices(kai_uart_devices,
+                               ARRAY_SIZE(kai_uart_devices));
+}
+
+static struct platform_device tegra_camera = {
+       .name = "tegra_camera",
+       .id = -1,
+};
+
+static struct platform_device *kai_spi_devices[] __initdata = {
+       &tegra_spi_device4,
+       &tegra_spi_device1,
+};
+
+static struct spi_clk_parent spi_parent_clk[] = {
+       [0] = {.name = "pll_p"},
+#ifndef CONFIG_TEGRA_PLLM_RESTRICTED
+       [1] = {.name = "pll_m"},
+       [2] = {.name = "clk_m"},
+#else
+       [1] = {.name = "clk_m"},
+#endif
+};
+
+static struct tegra_spi_platform_data kai_spi_pdata = {
+       .is_dma_based           = true,
+       .max_dma_buffer         = (16 * 1024),
+       .is_clkon_always        = false,
+       .max_rate               = 100000000,
+};
+
+static void __init kai_spi_init(void)
+{
+       int i;
+       struct clk *c;
+
+       for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) {
+               c = tegra_get_clock_by_name(spi_parent_clk[i].name);
+               if (IS_ERR_OR_NULL(c)) {
+                       pr_err("Not able to get the clock for %s\n",
+                                               spi_parent_clk[i].name);
+                       continue;
+               }
+               spi_parent_clk[i].parent_clk = c;
+               spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c);
+       }
+       kai_spi_pdata.parent_clk_list = spi_parent_clk;
+       kai_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk);
+       tegra_spi_device4.dev.platform_data = &kai_spi_pdata;
+       platform_add_devices(kai_spi_devices,
+                               ARRAY_SIZE(kai_spi_devices));
+
+}
+
+static struct resource tegra_rtc_resources[] = {
+       [0] = {
+               .start = TEGRA_RTC_BASE,
+               .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
+               .flags = IORESOURCE_MEM,
+       },
+       [1] = {
+               .start = INT_RTC,
+               .end = INT_RTC,
+               .flags = IORESOURCE_IRQ,
+       },
+};
+
+static struct platform_device tegra_rtc_device = {
+       .name = "tegra_rtc",
+       .id   = -1,
+       .resource = tegra_rtc_resources,
+       .num_resources = ARRAY_SIZE(tegra_rtc_resources),
+};
+
+static struct platform_device *kai_devices[] __initdata = {
+       &tegra_pmu_device,
+       &tegra_rtc_device,
+       &tegra_udc_device,
+#if defined(CONFIG_TEGRA_IOVMM_SMMU)
+       &tegra_smmu_device,
+#endif
+       &tegra_wdt_device,
+#if defined(CONFIG_TEGRA_AVP)
+       &tegra_avp_device,
+#endif
+       &tegra_camera,
+#if defined(CONFIG_CRYPTO_DEV_TEGRA_SE)
+       &tegra_se_device,
+#endif
+       &tegra_ahub_device,
+       &tegra_dam_device0,
+       &tegra_dam_device1,
+       &tegra_dam_device2,
+       &tegra_i2s_device1,
+       &tegra_i2s_device3,
+       &tegra_spdif_device,
+       &spdif_dit_device,
+       &bluetooth_dit_device,
+       &tegra_pcm_device,
+       &tegra_hda_device,
+#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
+       &tegra_aes_device,
+#endif
+};
+
+static __initdata struct tegra_clk_init_table spi_clk_init_table[] = {
+       /* name         parent          rate            enabled */
+       { "sbc1",       "pll_p",        72000000,       true},
+       { NULL,         NULL,           0,              0},
+};
+
+static __initdata struct tegra_clk_init_table touch_clk_init_table[] = {
+       /* name         parent          rate            enabled */
+       { "extern3",    "pll_p",        41000000,       true},
+       { "clk_out_3",  "extern3",      40800000,       true},
+       { NULL,         NULL,           0,              0},
+};
+
+static int __init kai_touch_init(void)
+{
+       int touch_id;
+
+       tegra_gpio_enable(KAI_TS_ID1);
+       tegra_gpio_enable(KAI_TS_ID2);
+
+       gpio_request(KAI_TS_ID1, "touch-id1");
+       gpio_direction_input(KAI_TS_ID1);
+
+       gpio_request(KAI_TS_ID2, "touch-id2");
+       gpio_direction_input(KAI_TS_ID2);
+
+       touch_id = gpio_get_value(KAI_TS_ID1) << 1;
+       touch_id |= gpio_get_value(KAI_TS_ID2);
+
+       pr_info("touch-id %d\n", touch_id);
+
+       /* Disable TS_ID GPIO to save power */
+       gpio_direction_output(KAI_TS_ID1, 0);
+       tegra_pinmux_set_pullupdown(KAI_TS_ID1_PG, TEGRA_PUPD_NORMAL);
+       tegra_pinmux_set_tristate(KAI_TS_ID1_PG, TEGRA_TRI_TRISTATE);
+       gpio_direction_output(KAI_TS_ID2, 0);
+       tegra_pinmux_set_pullupdown(KAI_TS_ID2_PG, TEGRA_PUPD_NORMAL);
+       tegra_pinmux_set_tristate(KAI_TS_ID2_PG, TEGRA_TRI_TRISTATE);
+
+       switch (touch_id) {
+       case 0:
+               pr_info("Raydium PCB based touch init\n");
+               tegra_clk_init_from_table(spi_clk_init_table);
+               touch_init_raydium();
+               break;
+       case 1:
+               pr_info("Raydium On-Board touch init\n");
+               tegra_clk_init_from_table(spi_clk_init_table);
+               tegra_clk_init_from_table(touch_clk_init_table);
+               clk_enable(tegra_get_clock_by_name("clk_out_3"));
+
+               touch_init_raydium();
+               break;
+       case 3:
+               pr_info("Synaptics PCB based touch init\n");
+               touch_init_synaptics_kai();
+               break;
+       default:
+               pr_err("touch_id error, no touch %d\n", touch_id);
+       }
+       return 0;
+}
+
+static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
+       [0] = {
+                       .phy_config = &utmi_phy_config[0],
+                       .operating_mode = TEGRA_USB_HOST,
+                       .power_down_on_bus_suspend = 1,
+       },
+       [1] = {
+                       .phy_config = &utmi_phy_config[1],
+                       .operating_mode = TEGRA_USB_HOST,
+                       .power_down_on_bus_suspend = 1,
+       },
+};
+
+static struct tegra_otg_platform_data tegra_otg_pdata = {
+       .ehci_device = &tegra_ehci1_device,
+       .ehci_pdata = &tegra_ehci_pdata[0],
+};
+
+#ifdef CONFIG_USB_SUPPORT
+static struct usb_phy_plat_data tegra_usb_phy_pdata[] = {
+       [0] = {
+                       .instance = 0,
+                       .vbus_gpio = -1,
+       },
+       [1] = {
+                       .instance = 1,
+                       .vbus_gpio = -1,
+       },
+};
+
+static void kai_usb_init(void)
+{
+       tegra_usb_phy_init(tegra_usb_phy_pdata,
+                       ARRAY_SIZE(tegra_usb_phy_pdata));
+
+       tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
+       platform_device_register(&tegra_otg_device);
+
+       tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1];
+       platform_device_register(&tegra_ehci2_device);
+}
+#else
+static void kai_usb_init(void) { }
+#endif
+
+static void __init tegra_kai_init(void)
+{
+       tegra_thermal_init(&thermal_data);
+       tegra_clk_init_from_table(kai_clk_init_table);
+       kai_pinmux_init();
+       kai_i2c_init();
+       kai_spi_init();
+       kai_usb_init();
+#ifdef CONFIG_TEGRA_EDP_LIMITS
+       kai_edp_init();
+#endif
+       kai_uart_init();
+       kai_tsensor_init();
+       platform_add_devices(kai_devices, ARRAY_SIZE(kai_devices));
+       tegra_ram_console_debug_init();
+       kai_sdhci_init();
+       kai_regulator_init();
+       kai_suspend_init();
+       kai_power_off_init();
+       kai_touch_init();
+       kai_keys_init();
+       kai_panel_init();
+       kai_pins_state_init();
+       tegra_release_bootloader_fb();
+#ifdef CONFIG_TEGRA_WDT_RECOVERY
+       tegra_wdt_recovery_init();
+#endif
+}
+
+static void __init kai_ramconsole_reserve(unsigned long size)
+{
+       tegra_ram_console_debug_reserve(SZ_1M);
+}
+
+static void __init tegra_kai_reserve(void)
+{
+#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM)
+       /* support 1920X1200 with 24bpp */
+       tegra_reserve(0, SZ_8M + SZ_1M, SZ_8M + SZ_1M);
+#else
+       tegra_reserve(SZ_128M, SZ_8M, SZ_8M);
+#endif
+       kai_ramconsole_reserve(SZ_1M);
+}
+
+MACHINE_START(KAI, "kai")
+       .boot_params    = 0x80000100,
+       .map_io         = tegra_map_common_io,
+       .reserve        = tegra_kai_reserve,
+       .init_early     = tegra_init_early,
+       .init_irq       = tegra_init_irq,
+       .timer          = &tegra_timer,
+       .init_machine   = tegra_kai_init,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/board-kai.h b/arch/arm/mach-tegra/board-kai.h
new file mode 100644 (file)
index 0000000..9dbced7
--- /dev/null
@@ -0,0 +1,77 @@
+/*
+ * arch/arm/mach-tegra/board-kai.h
+ *
+ * Copyright (c) 2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef _MACH_TEGRA_BOARD_KAI_H
+#define _MACH_TEGRA_BOARD_KAI_H
+
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+#include <linux/mfd/max77663-core.h>
+#include "gpio-names.h"
+
+/* Processor Board  ID */
+#define BOARD_E1565    0xF41
+
+/* Board Fab version */
+#define BOARD_FAB_A00                  0x0
+#define BOARD_FAB_A01                  0x1
+#define BOARD_FAB_A02                  0x2
+#define BOARD_FAB_A03                  0x3
+#define BOARD_FAB_A04                  0x4
+#define BOARD_FAB_A05                  0x5
+
+/* External peripheral act as gpio */
+/* MAX77663 GPIO */
+#define MAX77663_GPIO_BASE     TEGRA_NR_GPIOS
+#define MAX77663_GPIO_END      (MAX77663_GPIO_BASE + MAX77663_GPIO_NR)
+
+/*****************Interrupt tables ******************/
+/* External peripheral act as interrupt controller */
+/* MAX77663 IRQs */
+#define MAX77663_IRQ_BASE      TEGRA_NR_IRQS
+#define MAX77663_IRQ_END       (MAX77663_IRQ_BASE + MAX77663_IRQ_NR)
+
+int kai_charge_init(void);
+int kai_regulator_init(void);
+int kai_suspend_init(void);
+int kai_sdhci_init(void);
+int kai_pinmux_init(void);
+int kai_panel_init(void);
+int kai_keys_init(void);
+int kai_pins_state_init(void);
+int kai_power_off_init(void);
+int kai_edp_init(void);
+void __init kai_tsensor_init(void);
+int __init touch_init_raydium(void);
+int __init touch_init_synaptics_kai(void);
+
+#define TOUCH_GPIO_IRQ_RAYDIUM_SPI      TEGRA_GPIO_PZ3
+#define TOUCH_GPIO_RST_RAYDIUM_SPI      TEGRA_GPIO_PN5
+
+#define SYNAPTICS_ATTN_GPIO             TEGRA_GPIO_PZ3
+#define SYNAPTICS_RESET_GPIO            TEGRA_GPIO_PN5
+
+#define KAI_TS_ID1      TEGRA_GPIO_PI7
+#define KAI_TS_ID2      TEGRA_GPIO_PC7
+#define KAI_TS_ID1_PG   TEGRA_PINGROUP_GMI_WAIT
+#define KAI_TS_ID2_PG   TEGRA_PINGROUP_GMI_WP_N
+
+#define TDIODE_OFFSET  (10000) /* in millicelsius */
+
+#endif
diff --git a/arch/arm/mach-tegra/board-touch-kai-raydium_spi.c b/arch/arm/mach-tegra/board-touch-kai-raydium_spi.c
new file mode 100644 (file)
index 0000000..d2c5d7e
--- /dev/null
@@ -0,0 +1,67 @@
+/*
+ * arch/arm/mach-tegra/board-touch-raydium_spi.c
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/spi/spi.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/platform_data/rm31080a_ts.h>
+
+#if defined(CONFIG_MACH_KAI)
+#include "board-kai.h"
+#endif
+
+/* Raydium touchscreen                     Driver data */
+/*-----------------------------------------------------*/
+
+struct rm_spi_ts_platform_data rm31080ts_data = {
+       .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI,
+};
+
+struct spi_board_info rm31080a_spi_board[] = {
+       {
+               .modalias = "rm_ts_spidev",
+               .bus_num = 0,
+               .chip_select = 0,
+               .irq = TEGRA_GPIO_TO_IRQ(TOUCH_GPIO_IRQ_RAYDIUM_SPI),
+               .max_speed_hz = 18*1000*1000,
+               .mode = SPI_MODE_0,
+               .platform_data = &rm31080ts_data,
+       },
+};
+
+int __init touch_init_raydium(void)
+{
+       tegra_gpio_enable(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
+       gpio_request(TOUCH_GPIO_IRQ_RAYDIUM_SPI, "raydium-irq");
+       gpio_direction_input(TOUCH_GPIO_IRQ_RAYDIUM_SPI);
+
+       tegra_gpio_enable(TOUCH_GPIO_RST_RAYDIUM_SPI);
+       gpio_request(TOUCH_GPIO_RST_RAYDIUM_SPI, "raydium-reset");
+       gpio_direction_output(TOUCH_GPIO_RST_RAYDIUM_SPI, 0);
+
+       msleep(1);
+       gpio_set_value(TOUCH_GPIO_RST_RAYDIUM_SPI, 1);
+       msleep(100);
+
+       spi_register_board_info(rm31080a_spi_board,
+                                       ARRAY_SIZE(rm31080a_spi_board));
+       return 0;
+}
diff --git a/arch/arm/mach-tegra/board-touch-kai-synaptics-spi.c b/arch/arm/mach-tegra/board-touch-kai-synaptics-spi.c
new file mode 100644 (file)
index 0000000..b4052c2
--- /dev/null
@@ -0,0 +1,103 @@
+/*
+ * arch/arm/mach-tegra/board-touch-synaptics-spi.c
+ *
+ * Copyright (C) 2010-2011 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/spi/spi.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/spi/spi.h>
+#include <linux/rmi.h>
+#include "board.h"
+#include "board-kai.h"
+
+#define SYNAPTICS_SPI_CS 0
+#define SYNAPTICS_BUTTON_CODES {KEY_HOME, KEY_BACK,}
+
+static unsigned char synaptics_button_codes[] = SYNAPTICS_BUTTON_CODES;
+
+static struct rmi_f19_button_map synaptics_button_map = {
+       .nbuttons = ARRAY_SIZE(synaptics_button_codes),
+       .map = synaptics_button_codes,
+};
+
+static int synaptics_touchpad_gpio_setup(void)
+{
+       tegra_gpio_enable(SYNAPTICS_ATTN_GPIO);
+       gpio_request(SYNAPTICS_ATTN_GPIO, "synaptics-irq");
+       gpio_direction_input(SYNAPTICS_ATTN_GPIO);
+
+       tegra_gpio_enable(SYNAPTICS_RESET_GPIO);
+       gpio_request(SYNAPTICS_RESET_GPIO, "synaptics-reset");
+       gpio_direction_output(SYNAPTICS_RESET_GPIO, 0);
+
+       msleep(1);
+       gpio_set_value(SYNAPTICS_RESET_GPIO, 1);
+       msleep(100);
+
+       return 0;
+}
+
+static struct rmi_device_platform_data synaptics_platformdata = {
+       .driver_name = "rmi_generic",
+       .irq = SYNAPTICS_ATTN_GPIO,
+       .irq_polarity = RMI_IRQ_ACTIVE_LOW,
+       .gpio_config = synaptics_touchpad_gpio_setup,
+       .spi_data = {
+               .block_delay_us = 15,
+               .read_delay_us = 15,
+               .write_delay_us = 2,
+       },
+       .axis_align = {
+               .flip_y = true,
+       },
+       .button_map = &synaptics_button_map,
+};
+
+struct spi_board_info synaptics_2002_spi_board[] = {
+       {
+               .modalias = "rmi_spi",
+               .bus_num = 0,
+               .chip_select = 0,
+               .irq = 999,  /* just to make sure this one is not being used */
+               .max_speed_hz = 1*1000*1000,
+               .mode = SPI_MODE_3,
+               .platform_data = &synaptics_platformdata,
+       },
+};
+
+int __init touch_init_synaptics_kai(void)
+{
+       pr_info("%s: registering synaptics_2002_spi_board\n", __func__);
+       pr_info("               modalias     = %s\n",
+                                       synaptics_2002_spi_board->modalias);
+       pr_info("               bus_num      = %d\n",
+                                       synaptics_2002_spi_board->bus_num);
+       pr_info("               chip_select  = %d\n",
+                                       synaptics_2002_spi_board->chip_select);
+       pr_info("               irq          = %d\n",
+                                       synaptics_2002_spi_board->irq);
+       pr_info("               max_speed_hz = %d\n",
+                                       synaptics_2002_spi_board->max_speed_hz);
+       pr_info("               mode         = %d\n",
+                                       synaptics_2002_spi_board->mode);
+
+       msleep(100);
+       spi_register_board_info(synaptics_2002_spi_board,
+                                       ARRAY_SIZE(synaptics_2002_spi_board));
+       return 0;
+}
index 5290a3d..e2a54cd 100644 (file)
@@ -352,8 +352,6 @@ struct early_suspend ventana_panel_early_suspender;
 
 static void ventana_panel_early_suspend(struct early_suspend *h)
 {
-       unsigned i;
-
        /* power down LCD, add use a black screen for HDMI */
        if (num_registered_fb > 0)
                fb_blank(registered_fb[0], FB_BLANK_POWERDOWN);
@@ -362,9 +360,14 @@ static void ventana_panel_early_suspend(struct early_suspend *h)
 #ifdef CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND
        cpufreq_save_default_governor();
        cpufreq_set_conservative_governor();
-       cpufreq_set_conservative_governor_param(
-               SET_CONSERVATIVE_GOVERNOR_UP_THRESHOLD,
-               SET_CONSERVATIVE_GOVERNOR_DOWN_THRESHOLD);
+        cpufreq_set_conservative_governor_param("up_threshold",
+                       SET_CONSERVATIVE_GOVERNOR_UP_THRESHOLD);
+
+       cpufreq_set_conservative_governor_param("down_threshold",
+                       SET_CONSERVATIVE_GOVERNOR_DOWN_THRESHOLD);
+
+       cpufreq_set_conservative_governor_param("freq_step",
+               SET_CONSERVATIVE_GOVERNOR_FREQ_STEP);
 #endif
 }
 
index 406a427..8598738 100644 (file)
@@ -116,7 +116,6 @@ static int ventana_ov2710_power_on(void)
 {
        gpio_direction_output(CAMERA_CSI_MUX_SEL_GPIO, 1);
        gpio_direction_output(AVDD_DSI_CSI_ENB_GPIO, 1);
-       gpio_direction_output(CAM3_LDO_SHUTDN_L_GPIO, 1);
        mdelay(5);
        gpio_direction_output(CAM3_PWR_DN_GPIO, 0);
        mdelay(5);
@@ -131,7 +130,6 @@ static int ventana_ov2710_power_off(void)
 {
        gpio_direction_output(CAM3_RST_L_GPIO, 0);
        gpio_direction_output(CAM3_PWR_DN_GPIO, 1);
-       gpio_direction_output(CAM3_LDO_SHUTDN_L_GPIO, 0);
        gpio_direction_output(AVDD_DSI_CSI_ENB_GPIO, 0);
        gpio_direction_output(CAMERA_CSI_MUX_SEL_GPIO, 0);
        return 0;
@@ -469,15 +467,14 @@ static struct tegra_camera_gpios ventana_camera_gpio_keys[] = {
        [7] = TEGRA_CAMERA_GPIO("cam2_pwdn", CAM2_PWR_DN_GPIO, false, 0),
        [8] = TEGRA_CAMERA_GPIO("cam2_rst_lo", CAM2_RST_L_GPIO, false, 1),
 
-       [9] = TEGRA_CAMERA_GPIO("cam3_ldo_shdn_lo", CAM3_LDO_SHUTDN_L_GPIO, false, 0),
-       [10] = TEGRA_CAMERA_GPIO("cam3_af_pwdn_lo", CAM3_AF_PWR_DN_L_GPIO, false, 0),
-       [11] = TEGRA_CAMERA_GPIO("cam3_pwdn", CAM3_PWR_DN_GPIO, false, 0),
-       [12] = TEGRA_CAMERA_GPIO("cam3_rst_lo", CAM3_RST_L_GPIO, false, 1),
+       [9] = TEGRA_CAMERA_GPIO("cam3_af_pwdn_lo", CAM3_AF_PWR_DN_L_GPIO, false, 0),
+       [10] = TEGRA_CAMERA_GPIO("cam3_pwdn", CAM3_PWR_DN_GPIO, false, 0),
+       [11] = TEGRA_CAMERA_GPIO("cam3_rst_lo", CAM3_RST_L_GPIO, false, 1),
 
-       [13] = TEGRA_CAMERA_GPIO("cam1_ldo_shdn_lo", CAM1_LDO_SHUTDN_L_GPIO, false, 0),
-       [14] = TEGRA_CAMERA_GPIO("cam1_af_pwdn_lo", CAM1_AF_PWR_DN_L_GPIO, false, 0),
-       [15] = TEGRA_CAMERA_GPIO("cam1_pwdn", CAM1_PWR_DN_GPIO, false, 0),
-       [16] = TEGRA_CAMERA_GPIO("cam1_rst_lo", CAM1_RST_L_GPIO, false, 1),
+       [12] = TEGRA_CAMERA_GPIO("cam1_ldo_shdn_lo", CAM1_LDO_SHUTDN_L_GPIO, false, 0),
+       [13] = TEGRA_CAMERA_GPIO("cam1_af_pwdn_lo", CAM1_AF_PWR_DN_L_GPIO, false, 0),
+       [14] = TEGRA_CAMERA_GPIO("cam1_pwdn", CAM1_PWR_DN_GPIO, false, 0),
+       [15] = TEGRA_CAMERA_GPIO("cam1_rst_lo", CAM1_RST_L_GPIO, false, 1),
 };
 
 int __init ventana_camera_late_init(void)
index 0976440..21278d1 100644 (file)
@@ -595,7 +595,7 @@ static void __init tegra_ventana_init(void)
        tegra_ehci2_device.dev.platform_data
                = &ventana_ehci2_ulpi_platform_data;
        platform_add_devices(ventana_devices, ARRAY_SIZE(ventana_devices));
-
+       tegra_ram_console_debug_init();
        ventana_sdhci_init();
        ventana_charge_init();
        ventana_regulator_init();
@@ -644,6 +644,7 @@ void __init tegra_ventana_reserve(void)
                pr_warn("Cannot reserve first 4K of memory for safety\n");
 
        tegra_reserve(SZ_256M, SZ_8M + SZ_1M, SZ_16M);
+       tegra_ram_console_debug_reserve(SZ_1M);
 }
 
 MACHINE_START(VENTANA, "ventana")
index e68d6bf..9bdde43 100644 (file)
@@ -320,9 +320,14 @@ static void whistler_panel_early_suspend(struct early_suspend *h)
 #ifdef CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND
        cpufreq_save_default_governor();
        cpufreq_set_conservative_governor();
-       cpufreq_set_conservative_governor_param(
-               SET_CONSERVATIVE_GOVERNOR_UP_THRESHOLD,
-               SET_CONSERVATIVE_GOVERNOR_DOWN_THRESHOLD);
+        cpufreq_set_conservative_governor_param("up_threshold",
+                       SET_CONSERVATIVE_GOVERNOR_UP_THRESHOLD);
+
+       cpufreq_set_conservative_governor_param("down_threshold",
+                       SET_CONSERVATIVE_GOVERNOR_DOWN_THRESHOLD);
+
+       cpufreq_set_conservative_governor_param("freq_step",
+               SET_CONSERVATIVE_GOVERNOR_FREQ_STEP);
 #endif
 }
 
index 081b4fe..22c2f98 100644 (file)
 #include "board-whistler.h"
 #include "gpio-names.h"
 
+/* Setting the drive strength of pins
+ * hsm: Enable High speed mode (ENABLE/DISABLE)
+ * Schimit: Enable/disable schimit (ENABLE/DISABLE)
+ * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8)
+ * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive
+ *                strength code. Value from 0 to 31.
+ * pullup_drive - drive up (rising edge)  - Driver Output Pull-Up drive
+ *                strength code. Value from 0 to 31.
+ * pulldn_slew -  Driver Output Pull-Up slew control code  - 2bit code
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ * pullup_slew -  Driver Output Pull-Down slew control code -
+ *                code 11 is least slewing of signal. code 00 is highest
+ *                slewing of the signal.
+ *                Value - FASTEST, FAST, SLOW, SLOWEST
+ */
+#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \
+       {                                               \
+               .pingroup = TEGRA_DRIVE_PINGROUP_##_name,   \
+               .hsm = TEGRA_HSM_##_hsm,                    \
+               .schmitt = TEGRA_SCHMITT_##_schmitt,        \
+               .drive = TEGRA_DRIVE_##_drive,              \
+               .pull_down = TEGRA_PULL_##_pulldn_drive,    \
+               .pull_up = TEGRA_PULL_##_pullup_drive,          \
+               .slew_rising = TEGRA_SLEW_##_pulldn_slew,   \
+               .slew_falling = TEGRA_SLEW_##_pullup_slew,      \
+       }
+
 #define DEFAULT_DRIVE(_name)                                   \
        {                                                       \
                .pingroup = TEGRA_DRIVE_PINGROUP_##_name,       \
                .slew_falling = TEGRA_SLEW_SLOWEST,             \
        }
 
-
 static __initdata struct tegra_drive_pingroup_config whistler_drive_pinmux[] = {
        DEFAULT_DRIVE(DBG),
        DEFAULT_DRIVE(DDC),
        DEFAULT_DRIVE(VI1),
        DEFAULT_DRIVE(VI2),
        DEFAULT_DRIVE(SDIO1),
+       SET_DRIVE(DAP2, DISABLE, ENABLE, DIV_1, 46, 46, SLOWEST, SLOWEST),
+       SET_DRIVE(DAP3, DISABLE, ENABLE, DIV_1, 46, 46, SLOWEST, SLOWEST),
 };
 
 static __initdata struct tegra_pingroup_config whistler_pinmux[] = {
index 031ab93..0a5ad71 100644 (file)
@@ -573,7 +573,7 @@ static void __init tegra_whistler_init(void)
        whistler_i2c_init();
        whistler_uart_init();
        platform_add_devices(whistler_devices, ARRAY_SIZE(whistler_devices));
-
+       tegra_ram_console_debug_init();
        whistler_sdhci_init();
        whistler_regulator_init();
        whistler_panel_init();
@@ -603,6 +603,7 @@ void __init tegra_whistler_reserve(void)
                pr_warn("Cannot reserve first 4K of memory for safety\n");
 
        tegra_reserve(SZ_160M, SZ_8M, SZ_16M);
+       tegra_ram_console_debug_reserve(SZ_1M);
 }
 
 MACHINE_START(WHISTLER, "whistler")
index 950ccdf..fc22b76 100644 (file)
@@ -102,13 +102,14 @@ void tegra_get_pmu_board_info(struct board_info *bi);
 void tegra_get_display_board_info(struct board_info *bi);
 void tegra_get_camera_board_info(struct board_info *bi);
 #ifdef CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND
-#define SET_CONSERVATIVE_GOVERNOR_UP_THRESHOLD 95
-#define SET_CONSERVATIVE_GOVERNOR_DOWN_THRESHOLD 50
+#define SET_CONSERVATIVE_GOVERNOR_UP_THRESHOLD                 95
+#define SET_CONSERVATIVE_GOVERNOR_DOWN_THRESHOLD       50
+#define SET_CONSERVATIVE_GOVERNOR_FREQ_STEP            3
 
 void cpufreq_save_default_governor(void);
 void cpufreq_restore_default_governor(void);
 void cpufreq_set_conservative_governor(void);
-void cpufreq_set_conservative_governor_param(int up_th, int down_th);
+void cpufreq_set_conservative_governor_param(char *name, int value);
 #endif
 int get_core_edp(void);
 enum panel_type get_panel_type(void);
index 41a4d3f..b47821e 100644 (file)
@@ -6,7 +6,7 @@
  * Author:
  *     Colin Cross <ccross@google.com>
  *
- * Copyright (C) 2010-2011, NVIDIA Corporation.
+ * Copyright (C) 2010-2012, NVIDIA Corporation.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -170,6 +170,9 @@ struct clk {
                        unsigned long                   fixed_rate;
                } pll;
                struct {
+                       unsigned long                   default_rate;
+               } pll_div;
+               struct {
                        u32                             sel;
                        u32                             reg_mask;
                } mux;
@@ -295,6 +298,12 @@ struct tegra_cpufreq_table_data {
 };
 struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void);
 unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate);
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+static inline int tegra_update_mselect_rate(unsigned long cpu_rate)
+{ return 0; }
+#else
+int tegra_update_mselect_rate(unsigned long cpu_rate);
+#endif
 #endif
 
 #endif
index 2acf4bd..b5c3622 100644 (file)
@@ -2,7 +2,7 @@
  * arch/arm/mach-tegra/common.c
  *
  * Copyright (C) 2010 Google, Inc.
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (C) 2010-2012 NVIDIA Corporation
  *
  * Author:
  *     Colin Cross <ccross@android.com>
@@ -133,9 +133,9 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
        { "pll_p",      NULL,           216000000,      true },
        { "pll_p_out1", "pll_p",        28800000,       true },
-       { "pll_p_out2", "pll_p",        48000000,       true },
+       { "pll_p_out2", "pll_p",        48000000,       false },
        { "pll_p_out3", "pll_p",        72000000,       true },
-       { "pll_p_out4", "pll_p",        108000000,      true },
+       { "pll_p_out4", "pll_p",        108000000,      false },
        { "pll_m",      "clk_m",        0,              true },
        { "pll_m_out1", "pll_m",        120000000,      true },
        { "sclk",       "pll_c_out1",   40000000,       true },
@@ -148,15 +148,16 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
        { "2d",         "pll_c",        0,              false },
        { "3d",         "pll_c",        0,              false },
 #else
-       { "pll_p",      NULL,           408000000,      true },
-       { "pll_p_out1", "pll_p",        9600000,        false },
+       { "pll_p",      NULL,           0,              true },
+       { "pll_p_out1", "pll_p",        0,              false },
        { "pll_p_out2", "pll_p",        48000000,       false },
-       { "pll_p_out3", "pll_p",        102000000,      true },
+       { "pll_p_out3", "pll_p",        0,              true },
        { "pll_m_out1", "pll_m",        275000000,      false },
        { "pll_p_out4", "pll_p",        102000000,      false },
        { "sclk",       "pll_p_out4",   102000000,      true },
        { "hclk",       "sclk",         102000000,      true },
        { "pclk",       "hclk",         51000000,       true },
+       { "wake.sclk",  NULL,           40000000,       true },
 #endif
 #else
        { "pll_p",      NULL,           216000000,      true },
@@ -180,9 +181,12 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
        { "sdmmc1",     "pll_p",        48000000,       false},
        { "sdmmc3",     "pll_p",        48000000,       false},
        { "sdmmc4",     "pll_p",        48000000,       false},
+       { "pll_a",      "pll_p_out1",   0,              false},
+       { "pll_a_out0", "pll_a",        0,              false},
 #ifndef CONFIG_ARCH_TEGRA_2x_SOC
        { "cbus",       "pll_c",        416000000,      false },
        { "pll_c_out1", "pll_c",        208000000,      false },
+       { "mselect",    "pll_p",        102000000,      true },
 #endif
        { NULL,         NULL,           0,              0},
 };
@@ -961,7 +965,7 @@ static void cpufreq_set_governor(char *governor)
        struct file *scaling_gov = NULL;
        mm_segment_t old_fs;
        char    buf[128];
-       int i = 0;
+       int i;
        loff_t offset = 0;
 
        if (governor == NULL)
@@ -976,9 +980,7 @@ static void cpufreq_set_governor(char *governor)
        {
                sprintf(buf, cpufreq_sysfs_place_holder, i);
                scaling_gov = filp_open(buf, O_RDWR, 0);
-               if (IS_ERR_OR_NULL(scaling_gov)) {
-                       pr_err("%s. Can't open %s\n", __func__, buf);
-               } else {
+               if (scaling_gov != NULL) {
                        if (scaling_gov->f_op != NULL &&
                                scaling_gov->f_op->write != NULL)
                                scaling_gov->f_op->write(scaling_gov,
@@ -989,6 +991,8 @@ static void cpufreq_set_governor(char *governor)
                                pr_err("f_op might be null\n");
 
                        filp_close(scaling_gov, NULL);
+               } else {
+                       pr_err("%s. Can't open %s\n", __func__, buf);
                }
        }
        set_fs(old_fs);
@@ -1008,9 +1012,7 @@ void cpufreq_save_default_governor(void)
        buf[127] = 0;
        sprintf(buf, cpufreq_sysfs_place_holder,0);
        scaling_gov = filp_open(buf, O_RDONLY, 0);
-       if (IS_ERR_OR_NULL(scaling_gov)) {
-               pr_err("%s. Can't open %s\n", __func__, buf);
-       } else {
+       if (scaling_gov != NULL) {
                if (scaling_gov->f_op != NULL &&
                        scaling_gov->f_op->read != NULL)
                        scaling_gov->f_op->read(scaling_gov,
@@ -1021,6 +1023,8 @@ void cpufreq_save_default_governor(void)
                        pr_err("f_op might be null\n");
 
                filp_close(scaling_gov, NULL);
+       } else {
+               pr_err("%s. Can't open %s\n", __func__, buf);
        }
        set_fs(old_fs);
 }
@@ -1030,57 +1034,33 @@ void cpufreq_restore_default_governor(void)
        cpufreq_set_governor(cpufreq_gov_default);
 }
 
-void cpufreq_set_conservative_governor_param(int up_th, int down_th)
+void cpufreq_set_conservative_governor_param(char *name, int value)
 {
        struct file *gov_param = NULL;
-       static char buf[128],parm[8];
-       loff_t offset = 0;
        mm_segment_t old_fs;
-
-       if (up_th <= down_th) {
-               printk(KERN_ERR "%s: up_th(%d) is lesser than down_th(%d)\n",
-                       __func__, up_th, down_th);
-               return;
-       }
+       static char buf[128], param_value[8];
+       loff_t offset = 0;
 
        /* change to KERNEL_DS address limit */
        old_fs = get_fs();
        set_fs(KERNEL_DS);
 
-       sprintf(parm, "%d", up_th);
-       sprintf(buf, cpufreq_gov_conservative_param ,"up_threshold");
-       gov_param = filp_open(buf, O_RDONLY, 0);
-       if (IS_ERR_OR_NULL(gov_param)) {
-               pr_err("%s. Can't open %s\n", __func__, buf);
-       } else {
+       sprintf(param_value, "%d", value);
+       sprintf(buf, cpufreq_gov_conservative_param, name);
+       gov_param = filp_open(buf, O_RDWR, 0);
+       if (gov_param != NULL) {
                if (gov_param->f_op != NULL &&
                        gov_param->f_op->write != NULL)
                        gov_param->f_op->write(gov_param,
-                                       parm,
-                                       strlen(parm),
+                                       param_value,
+                                       strlen(param_value),
                                        &offset);
                else
                        pr_err("f_op might be null\n");
 
                filp_close(gov_param, NULL);
-       }
-
-       sprintf(parm, "%d", down_th);
-       sprintf(buf, cpufreq_gov_conservative_param ,"down_threshold");
-       gov_param = filp_open(buf, O_RDONLY, 0);
-       if (IS_ERR_OR_NULL(gov_param)) {
-               pr_err("%s. Can't open %s\n", __func__, buf);
        } else {
-               if (gov_param->f_op != NULL &&
-                       gov_param->f_op->write != NULL)
-                       gov_param->f_op->write(gov_param,
-                                       parm,
-                                       strlen(parm),
-                                       &offset);
-               else
-                       pr_err("f_op might be null\n");
-
-               filp_close(gov_param, NULL);
+               pr_err("%s. Can't open %s\n", __func__, buf);
        }
        set_fs(old_fs);
 }
index 24ed5d2..de290ce 100644 (file)
@@ -473,8 +473,20 @@ static int tegra_update_cpu_speed(unsigned long rate)
         * Vote on memory bus frequency based on cpu frequency
         * This sets the minimum frequency, display or avp may request higher
         */
-       if (freqs.old < freqs.new)
-               clk_set_rate(emc_clk, tegra_emc_to_cpu_ratio(freqs.new));
+       if (freqs.old < freqs.new) {
+               ret = tegra_update_mselect_rate(freqs.new);
+               if (ret) {
+                       pr_err("cpu-tegra: Failed to scale mselect for cpu"
+                              " frequency %u kHz\n", freqs.new);
+                       return ret;
+               }
+               ret = clk_set_rate(emc_clk, tegra_emc_to_cpu_ratio(freqs.new));
+               if (ret) {
+                       pr_err("cpu-tegra: Failed to scale emc for cpu"
+                              " frequency %u kHz\n", freqs.new);
+                       return ret;
+               }
+       }
 
        for_each_online_cpu(freqs.cpu)
                cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
@@ -494,8 +506,10 @@ static int tegra_update_cpu_speed(unsigned long rate)
        for_each_online_cpu(freqs.cpu)
                cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 
-       if (freqs.old > freqs.new)
+       if (freqs.old > freqs.new) {
                clk_set_rate(emc_clk, tegra_emc_to_cpu_ratio(freqs.new));
+               tegra_update_mselect_rate(freqs.new);
+       }
 
        return 0;
 }
index bb10c10..39bc04b 100644 (file)
@@ -27,6 +27,7 @@
 #include <linux/platform_data/tegra_usb.h>
 #include <linux/tegra_avp.h>
 #include <linux/nvhost.h>
+#include <linux/clk.h>
 #include <asm/pmu.h>
 #include <mach/irqs.h>
 #include <mach/iomap.h>
@@ -1324,7 +1325,7 @@ struct platform_device tegra_das_device = {
 };
 #endif
 
-#if defined(CONFIG_TEGRA_IOVMM_GART)
+#if defined(CONFIG_TEGRA_IOVMM_GART) || defined(CONFIG_TEGRA_IOMMU_GART)
 static struct resource tegra_gart_resources[] = {
        [0] = {
                .name   = "mc",
@@ -1733,3 +1734,20 @@ struct platform_device tegra_nvmap_device = {
        .name   = "tegra-nvmap",
        .id     = -1,
 };
+
+void tegra_init_debug_uart_rate(void)
+{
+       unsigned int uartclk;
+       struct clk *debug_uart_parent = clk_get_sys(NULL, "pll_p");
+
+       BUG_ON(IS_ERR(debug_uart_parent));
+       uartclk = clk_get_rate(debug_uart_parent);
+
+       debug_uarta_platform_data[0].uartclk = uartclk;
+       debug_uartb_platform_data[0].uartclk = uartclk;
+       debug_uartc_platform_data[0].uartclk = uartclk;
+       debug_uartd_platform_data[0].uartclk = uartclk;
+#if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
+       debug_uarte_platform_data[0].uartclk = uartclk;
+#endif
+}
index 6d7c7ca..ff93216 100644 (file)
@@ -5,7 +5,7 @@
  *     Colin Cross <ccross@android.com>
  *     Erik Gilling <ccross@android.com>
  *
- * Copyright (C) 2010-2011 NVIDIA Corporation.
+ * Copyright (C) 2010-2012 NVIDIA Corporation.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -126,4 +126,7 @@ extern struct platform_device debug_uarte_device;
 
 extern struct nvhost_device tegra_disp1_device;
 extern struct platform_device tegra_nvmap_device;
+
+void tegra_init_debug_uart_rate(void);
+
 #endif
index caca9d8..4137a8f 100644 (file)
@@ -324,6 +324,7 @@ struct tegra_dc_out {
        int                             dcc_bus;
        int                             hotplug_gpio;
        const char                      *parent_clk;
+       const char                      *parent_clk_backup;
 
        unsigned                        max_pixclock;
        unsigned                        order;
index 9665858..4a8ac6b 100644 (file)
@@ -7,7 +7,7 @@
  *     Colin Cross <ccross@google.com>
  *     Erik Gilling <konkers@google.com>
  *
- * Copyright (C) 2010-2011 NVIDIA Corporation
+ * Copyright (C) 2010-2012 NVIDIA Corporation
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
 #define DEBUG_UART_RST_CLR_REG         0
 #define DEBUG_UART_RST_CLR_BIT         0
 #endif
+#define PLLP_BASE                      (TEGRA_CLK_RESET_BASE + 0x0a0)
+#define PLLP_BASE_OVERRIDE             (1 << 28)
+#define PLLP_BASE_DIVP_SHIFT           20
+#define PLLP_BASE_DIVP_MASK            (0x7 << 20)
+#define PLLP_BASE_DIVN_SHIFT           8
+#define PLLP_BASE_DIVN_MASK            (0x3FF << 8)
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-#define DEBUG_UART_DLL                 0x75
-#else
-#define DEBUG_UART_DLL                 0xdd
-#endif
+#define DEBUG_UART_DLL_216             0x75
+#define DEBUG_UART_DLL_408             0xdd
+#define DEBUG_UART_DLL_204             0x6f
 
 static void putc(int c)
 {
@@ -104,6 +108,8 @@ static inline void arch_decomp_setup(void)
        volatile u8 *uart = (volatile u8 *)TEGRA_DEBUG_UART_BASE;
        int shift = 2;
        volatile u32 *addr;
+       u8 uart_dll = DEBUG_UART_DLL_216;
+       u32 val;
 
        if (uart == NULL)
                return;
@@ -124,9 +130,37 @@ static inline void arch_decomp_setup(void)
 
        konk_delay(5);
 
+       /*
+        * On Tegra2 platforms PLLP always run at 216MHz
+        * On Tegra3 platforms PLLP can run at 216MHz, 204MHz, or 408MHz
+        * Discrimantion algorithm below assumes that PLLP is configured
+        * according to h/w recomendations with update rate 1MHz or 1.2MHz
+        * depending on oscillator frequency
+        */
+       addr = (volatile u32 *)PLLP_BASE;
+       val = *addr;
+       if (val & PLLP_BASE_OVERRIDE) {
+               u32 p = (val & PLLP_BASE_DIVP_MASK) >> PLLP_BASE_DIVP_SHIFT;
+               val = (val & PLLP_BASE_DIVN_MASK) >> (PLLP_BASE_DIVN_SHIFT + p);
+               switch (val) {
+               case 170:
+               case 204:
+                       uart_dll = DEBUG_UART_DLL_204;
+                       break;
+               case 340:
+               case 408:
+                       uart_dll = DEBUG_UART_DLL_408;
+                       break;
+               case 180:
+               case 216:
+               default:
+                       break;
+               }
+       }
+
        /* Set up debug UART. */
        uart[UART_LCR << shift] |= UART_LCR_DLAB;
-       uart[UART_DLL << shift] = DEBUG_UART_DLL;
+       uart[UART_DLL << shift] = uart_dll;
        uart[UART_DLM << shift] = 0x0;
        uart[UART_LCR << shift] = 3;
 }
index ab2459b..896e1e9 100644 (file)
@@ -44,7 +44,7 @@
 #define MC_LA_EPP_0            0x300
 #define MC_LA_EPP_1            0x304
 #define MC_LA_G2_0             0x308
-#define MC_LA_G2_1             0x304
+#define MC_LA_G2_1             0x30c
 #define MC_LA_HC_0             0x310
 #define MC_LA_HC_1             0x314
 #define MC_LA_HDA_0            0x318
index c665220..780fe2a 100644 (file)
@@ -587,7 +587,7 @@ static int tegra_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
        return INT_PCIE_INTR;
 }
 
-static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
+static struct pci_bus *tegra_pcie_scan_bus(int nr,
                                                  struct pci_sys_data *sys)
 {
        struct tegra_pcie_port *pp;
@@ -601,7 +601,7 @@ static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
        return pci_scan_bus(sys->busnr, &tegra_pcie_ops, sys);
 }
 
-static struct hw_pci tegra_pcie_hw __initdata = {
+static struct hw_pci tegra_pcie_hw = {
        .nr_controllers = MAX_PCIE_SUPPORTED_PORTS,
        .setup          = tegra_pcie_setup,
        .scan           = tegra_pcie_scan_bus,
index 2de6f87..48f27cf 100644 (file)
@@ -440,10 +440,7 @@ void tegra_lp0_cpu_mode(bool enter)
 #define PMC_DPD_SAMPLE                 0x20
 
 struct tegra_io_dpd tegra_list_io_dpd[] = {
-       /* sd dpd bits in dpd2 register */
-       IO_DPD_INFO("sdhci-tegra.0",    1,      1), /* SDMMC1 */
-       IO_DPD_INFO("sdhci-tegra.2",    1,      2), /* SDMMC3 */
-       IO_DPD_INFO("sdhci-tegra.3",    1,      3), /* SDMMC4 */
+/* Empty DPD list - sd dpd entries removed */
 };
 
 struct tegra_io_dpd *tegra_io_dpd_get(struct device *dev)
@@ -474,7 +471,7 @@ void tegra_io_dpd_enable(struct tegra_io_dpd *hnd)
        unsigned int dpd_status;
        unsigned int dpd_enable_lsb;
 
-       if (WARN_ON(!hnd))
+       if ((!hnd))
                return;
        spin_lock(&tegra_io_dpd_lock);
        dpd_enable_lsb = (hnd->io_dpd_reg_index) ? APBDEV_DPD2_ENABLE_LSB :
@@ -503,7 +500,7 @@ void tegra_io_dpd_disable(struct tegra_io_dpd *hnd)
        unsigned int dpd_status;
        unsigned int dpd_enable_lsb;
 
-       if (WARN_ON(!hnd))
+       if ((!hnd))
                return;
        spin_lock(&tegra_io_dpd_lock);
        dpd_enable_lsb = (hnd->io_dpd_reg_index) ? APBDEV_DPD2_ENABLE_LSB :
index edcb283..61a93ee 100644 (file)
@@ -33,6 +33,7 @@
 #include <linux/debugfs.h>
 #include <linux/delay.h>
 #include <linux/suspend.h>
+#include <linux/earlysuspend.h>
 #include <linux/slab.h>
 #include <linux/serial_reg.h>
 #include <linux/seq_file.h>
@@ -41,6 +42,7 @@
 #include <linux/vmalloc.h>
 #include <linux/memblock.h>
 #include <linux/console.h>
+#include <linux/pm_qos_params.h>
 
 #include <asm/cacheflush.h>
 #include <asm/cpu_pm.h>
@@ -167,19 +169,15 @@ struct suspend_context tegra_sctx;
 #define MC_SECURITY_SIZE       0x70
 #define MC_SECURITY_CFG2       0x7c
 
+#define AWAKE_CPU_FREQ_MIN     100000
+static struct pm_qos_request_list awake_cpu_freq_req;
+
 struct dvfs_rail *tegra_cpu_rail;
 static struct dvfs_rail *tegra_core_rail;
 static struct clk *tegra_pclk;
 static const struct tegra_suspend_platform_data *pdata;
 static enum tegra_suspend_mode current_suspend_mode = TEGRA_SUSPEND_NONE;
 
-static const char *tegra_suspend_name[TEGRA_MAX_SUSPEND_MODE] = {
-       [TEGRA_SUSPEND_NONE]    = "none",
-       [TEGRA_SUSPEND_LP2]     = "lp2",
-       [TEGRA_SUSPEND_LP1]     = "lp1",
-       [TEGRA_SUSPEND_LP0]     = "lp0",
-};
-
 #if defined(CONFIG_TEGRA_CLUSTER_CONTROL) && INSTRUMENT_CLUSTER_SWITCH
 enum tegra_cluster_switch_time_id {
        tegra_cluster_switch_time_id_start = 0,
@@ -209,6 +207,13 @@ static unsigned long
 #endif
 
 #ifdef CONFIG_PM_SLEEP
+static const char *tegra_suspend_name[TEGRA_MAX_SUSPEND_MODE] = {
+       [TEGRA_SUSPEND_NONE]    = "none",
+       [TEGRA_SUSPEND_LP2]     = "lp2",
+       [TEGRA_SUSPEND_LP1]     = "lp1",
+       [TEGRA_SUSPEND_LP0]     = "lp0",
+};
+
 unsigned long tegra_cpu_power_good_time(void)
 {
        if (WARN_ON_ONCE(!pdata))
@@ -519,7 +524,7 @@ bool tegra_set_cpu_in_lp2(int cpu)
        if ((cpu == 0) && cpumask_equal(&tegra_in_lp2, cpu_online_mask))
                last_cpu = true;
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
-       else
+       else if (cpu == 1)
                tegra2_cpu_set_resettable_soon();
 #endif
 
@@ -763,6 +768,10 @@ static int tegra_suspend_enter(suspend_state_t state)
        read_persistent_clock(&ts_entry);
 
        ret = tegra_suspend_dram(current_suspend_mode, 0);
+       if (ret) {
+               pr_info("Aborting suspend, tegra_suspend_dram error=%d\n", ret);
+               goto abort_suspend;
+       }
 
        read_persistent_clock(&ts_exit);
 
@@ -776,6 +785,7 @@ static int tegra_suspend_enter(suspend_state_t state)
                        tegra_dvfs_rail_pause(tegra_core_rail, delta, true);
        }
 
+abort_suspend:
        if (pdata && pdata->board_resume)
                pdata->board_resume(current_suspend_mode, TEGRA_RESUME_AFTER_PERIPHERAL);
 
@@ -810,7 +820,13 @@ static void tegra_suspend_check_pwr_stats(void)
 
 int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags)
 {
-       BUG_ON(mode < 0 || mode >= TEGRA_MAX_SUSPEND_MODE);
+       int err = 0;
+
+       if (WARN_ON(mode <= TEGRA_SUSPEND_NONE ||
+               mode >= TEGRA_MAX_SUSPEND_MODE)) {
+               err = -ENXIO;
+               goto fail;
+       }
 
        if ((mode == TEGRA_SUSPEND_LP0) && !tegra_pm_irq_lp0_allowed()) {
                pr_info("LP0 not used due to unsupported wakeup events\n");
@@ -892,7 +908,8 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags)
 
        tegra_common_resume();
 
-       return 0;
+fail:
+       return err;
 }
 
 /*
@@ -950,6 +967,11 @@ static ssize_t suspend_mode_store(struct kobject *kobj,
        len = name_ptr - buf;
        if (!len)
                goto bad_name;
+       /* TEGRA_SUSPEND_NONE not allowed as suspend state */
+       if (!(strncmp(buf, tegra_suspend_name[TEGRA_SUSPEND_NONE], len))) {
+               pr_info("Illegal tegra suspend state: %s\n", buf);
+               goto bad_name;
+       }
 
        for (new_mode = TEGRA_SUSPEND_NONE; \
                        new_mode < TEGRA_MAX_SUSPEND_MODE; ++new_mode) {
@@ -967,9 +989,7 @@ static struct kobj_attribute suspend_mode_attribute =
        __ATTR(mode, 0644, suspend_mode_show, suspend_mode_store);
 
 static struct kobject *suspend_kobj;
-#endif
 
-#ifdef CONFIG_PM_SLEEP
 static int tegra_pm_enter_suspend(void)
 {
        pr_info("Entering suspend state %s\n", lp_state[current_suspend_mode]);
@@ -1005,6 +1025,9 @@ void __init tegra_init_suspend(struct tegra_suspend_platform_data *plat)
 
        tegra_cpu_rail = tegra_dvfs_get_rail_by_name("vdd_cpu");
        tegra_core_rail = tegra_dvfs_get_rail_by_name("vdd_core");
+       pm_qos_add_request(&awake_cpu_freq_req, PM_QOS_CPU_FREQ_MIN,
+                          AWAKE_CPU_FREQ_MIN);
+
        tegra_pclk = clk_get_sys(NULL, "pclk");
        BUG_ON(IS_ERR(tegra_pclk));
        pdata = plat;
@@ -1242,3 +1265,35 @@ static int tegra_debug_uart_syscore_init(void)
        return 0;
 }
 arch_initcall(tegra_debug_uart_syscore_init);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+static struct clk *clk_wake;
+
+static void pm_early_suspend(struct early_suspend *h)
+{
+       if (clk_wake)
+               clk_disable(clk_wake);
+       pm_qos_update_request(&awake_cpu_freq_req, PM_QOS_DEFAULT_VALUE);
+}
+
+static void pm_late_resume(struct early_suspend *h)
+{
+       if (clk_wake)
+               clk_enable(clk_wake);
+       pm_qos_update_request(&awake_cpu_freq_req, (s32)AWAKE_CPU_FREQ_MIN);
+}
+
+static struct early_suspend pm_early_suspender = {
+               .suspend = pm_early_suspend,
+               .resume = pm_late_resume,
+};
+
+static int pm_init_wake_behavior(void)
+{
+       clk_wake = tegra_get_clock_by_name("wake.sclk");
+       register_early_suspend(&pm_early_suspender);
+       return 0;
+}
+
+late_initcall(pm_init_wake_behavior);
+#endif
index 05cdc1f..c7aeb9a 100644 (file)
@@ -666,9 +666,6 @@ static int down_threshold_set(void *data, u64 val)
        struct actmon_dev *dev = data;
        unsigned int down_threshold = (unsigned int)val;
 
-       if (down_threshold < 0)
-               down_threshold = 0;
-
        spin_lock_irqsave(&dev->lock, flags);
 
        if (down_threshold >= dev->boost_up_threshold)
index 3fe531f..1298540 100644 (file)
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/tegra3_clocks.c
  *
- * Copyright (C) 2010-2011 NVIDIA Corporation
+ * Copyright (C) 2010-2012 NVIDIA Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
 #define ROUND_DIVIDER_UP       0
 #define ROUND_DIVIDER_DOWN     1
 
-#ifdef CONFIG_TEGRA_SILICON_PLATFORM
-#define PLLP_FIXED_RATE                        408000000
-#else
-#define PLLP_FIXED_RATE                        216000000
-#endif
-
-/* sbus threshold must be exact factor of pll_p */
-#define SBUS_THRESHOLD_RATE            (PLLP_FIXED_RATE / 2)
-
-/*
- * Backup rate targets for each CPU mode is selected below Fmax(Vmin), and
- * high enough to avoid voltage droop when CPU clock is switched between
- * backup and main clock sources. Actual backup rates will be rounded based
- * on backup source fixed frequency. Maximum stay-on-backup rate will be set
- * as a minimum of G and LP backup rates to be supported in both modes.
- */
-#define CPU_G_BACKUP_RATE_TARGET       440000000
-#define CPU_G_BACKUP_RATE_DIV          \
-        DIV_ROUND_UP(PLLP_FIXED_RATE, CPU_G_BACKUP_RATE_TARGET)
-#define CPU_G_BACKUP_RATE              \
-        (PLLP_FIXED_RATE / CPU_G_BACKUP_RATE_DIV)
-
-#define CPU_LP_BACKUP_RATE_TARGET      220000000
-#define CPU_LP_BACKUP_RATE_DIV         \
-        DIV_ROUND_UP(PLLP_FIXED_RATE, CPU_LP_BACKUP_RATE_TARGET)
-#define CPU_LP_BACKUP_RATE             \
-        (PLLP_FIXED_RATE / CPU_LP_BACKUP_RATE_DIV)
-
-#define CPU_STAY_ON_BACKUP_MAX         \
-        min(CPU_G_BACKUP_RATE, CPU_LP_BACKUP_RATE)
+/* PLLP default fixed rate in h/w controlled mode */
+#define PLLP_DEFAULT_FIXED_RATE                216000000
 
 /* Threshold to engage CPU clock skipper during CPU rate change */
 #define SKIPPER_ENGAGE_RATE             800000000
 
 static bool tegra3_clk_is_parent_allowed(struct clk *c, struct clk *p);
-
+static void tegra3_pllp_init_dependencies(unsigned long pllp_rate);
 static int tegra3_clk_shared_bus_update(struct clk *bus);
 
+static unsigned long cpu_stay_on_backup_max;
 static struct clk *emc_bridge;
 
 static bool detach_shared_bus;
@@ -391,8 +364,10 @@ static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE);
 
 /*
  * Some peripheral clocks share an enable bit, so refcount the enable bits
- * in registers CLK_ENABLE_L, ... CLK_ENABLE_W
+ * in registers CLK_ENABLE_L, ... CLK_ENABLE_W, and protect refcount updates
+ * with lock
  */
+static DEFINE_SPINLOCK(periph_refcount_lock);
 static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
 
 #define clk_writel(value, reg) \
@@ -932,7 +907,7 @@ static int tegra3_cpu_clk_set_rate(struct clk *c, unsigned long rate)
                }
        }
 
-       if (rate <= CPU_STAY_ON_BACKUP_MAX) {
+       if (rate <= cpu_stay_on_backup_max) {
                ret = clk_set_rate(c->parent, rate);
                if (ret)
                        pr_err("Failed to set cpu rate %lu on backup source\n",
@@ -1525,6 +1500,8 @@ static void tegra3_pll_clk_init(struct clk *c)
        if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
                const struct clk_pll_freq_table *sel;
                unsigned long input_rate = clk_get_rate(c->parent);
+               c->u.pll.fixed_rate = PLLP_DEFAULT_FIXED_RATE;
+
                for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
                        if (sel->input_rate == input_rate &&
                                sel->output_rate == c->u.pll.fixed_rate) {
@@ -1546,10 +1523,10 @@ static void tegra3_pll_clk_init(struct clk *c)
                else
                        c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
                                        PLL_BASE_DIVP_SHIFT));
-               if (c->flags & PLL_FIXED) {
-                       unsigned long rate = clk_get_rate_locked(c);
-                       BUG_ON(rate != c->u.pll.fixed_rate);
-               }
+       }
+
+       if (c->flags & PLL_FIXED) {
+               c->u.pll.fixed_rate = clk_get_rate_locked(c);
        }
 
        if (c->flags & PLLU) {
@@ -1665,6 +1642,13 @@ static int tegra3_pll_clk_set_rate(struct clk *c, unsigned long rate)
                        cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
                        break;
                default:
+                       if (c->parent->flags & DIV_U71_FIXED) {
+                               /* PLLP_OUT1 rate is not in PLLA table */
+                               pr_warn("%s: failed %s ref/out rates %lu/%lu\n",
+                                       __func__, c->name, input_rate, rate);
+                               cfreq = input_rate/(input_rate/1000000);
+                               break;
+                       }
                        pr_err("%s: Unexpected reference rate %lu\n",
                               __func__, input_rate);
                        BUG();
@@ -1736,6 +1720,26 @@ static struct clk_ops tegra_pll_ops = {
        .set_rate               = tegra3_pll_clk_set_rate,
 };
 
+static void tegra3_pllp_clk_init(struct clk *c)
+{
+       tegra3_pll_clk_init(c);
+       tegra3_pllp_init_dependencies(c->u.pll.fixed_rate);
+}
+
+static void tegra3_pllp_clk_resume(struct clk *c)
+{
+       unsigned long rate = c->u.pll.fixed_rate;
+       tegra3_pll_clk_init(c);
+       BUG_ON(rate != c->u.pll.fixed_rate);
+}
+
+static struct clk_ops tegra_pllp_ops = {
+       .init                   = tegra3_pllp_clk_init,
+       .enable                 = tegra3_pll_clk_enable,
+       .disable                = tegra3_pll_clk_disable,
+       .set_rate               = tegra3_pll_clk_set_rate,
+};
+
 static int
 tegra3_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
 {
@@ -1906,7 +1910,10 @@ static struct clk_ops tegra_plle_ops = {
        .disable                = tegra3_plle_clk_disable,
 };
 
-/* Clock divider ops */
+/* Clock divider ops (non-atomic shared register access) */
+static DEFINE_SPINLOCK(pll_div_lock);
+
+static int tegra3_pll_div_clk_set_rate(struct clk *c, unsigned long rate);
 static void tegra3_pll_div_clk_init(struct clk *c)
 {
        if (c->flags & DIV_U71) {
@@ -1917,6 +1924,12 @@ static void tegra3_pll_div_clk_init(struct clk *c)
                if (!(val & PLL_OUT_RESET_DISABLE))
                        c->state = OFF;
 
+               if (c->u.pll_div.default_rate) {
+                       int ret = tegra3_pll_div_clk_set_rate(
+                                       c, c->u.pll_div.default_rate);
+                       if (!ret)
+                               return;
+               }
                divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
                c->div = (divu71 + 2);
                c->mul = 2;
@@ -1939,9 +1952,11 @@ static int tegra3_pll_div_clk_enable(struct clk *c)
 {
        u32 val;
        u32 new_val;
+       unsigned long flags;
 
        pr_debug("%s: %s\n", __func__, c->name);
        if (c->flags & DIV_U71) {
+               spin_lock_irqsave(&pll_div_lock, flags);
                val = clk_readl(c->reg);
                new_val = val >> c->reg_shift;
                new_val &= 0xFFFF;
@@ -1951,6 +1966,7 @@ static int tegra3_pll_div_clk_enable(struct clk *c)
                val &= ~(0xFFFF << c->reg_shift);
                val |= new_val << c->reg_shift;
                clk_writel_delay(val, c->reg);
+               spin_unlock_irqrestore(&pll_div_lock, flags);
                return 0;
        } else if (c->flags & DIV_2) {
                return 0;
@@ -1962,9 +1978,11 @@ static void tegra3_pll_div_clk_disable(struct clk *c)
 {
        u32 val;
        u32 new_val;
+       unsigned long flags;
 
        pr_debug("%s: %s\n", __func__, c->name);
        if (c->flags & DIV_U71) {
+               spin_lock_irqsave(&pll_div_lock, flags);
                val = clk_readl(c->reg);
                new_val = val >> c->reg_shift;
                new_val &= 0xFFFF;
@@ -1974,6 +1992,7 @@ static void tegra3_pll_div_clk_disable(struct clk *c)
                val &= ~(0xFFFF << c->reg_shift);
                val |= new_val << c->reg_shift;
                clk_writel_delay(val, c->reg);
+               spin_unlock_irqrestore(&pll_div_lock, flags);
        }
 }
 
@@ -1983,12 +2002,14 @@ static int tegra3_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
        u32 new_val;
        int divider_u71;
        unsigned long parent_rate = clk_get_rate(c->parent);
+       unsigned long flags;
 
        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
        if (c->flags & DIV_U71) {