ARM: tegra: clock: Changed PLLE settings
Alex Frid [Sat, 19 Mar 2011 01:08:54 +0000 (18:08 -0700)]
Bug 792743

Original-Change-Id: I9ea94faefa01406ff16d2b78eab251b3b35cae9a
Reviewed-on: http://git-master/r/23733
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yen Lin <yelin@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I4d0f4de7e5d32050010e368aef05f8b6bc20f6e1

Rebase-Id: Rb3672da6fe79766e0b865a16f1463989c7aeb1fe

arch/arm/mach-tegra/tegra3_clocks.c

index 452516c..48cfebb 100644 (file)
@@ -2572,7 +2572,7 @@ static struct clk tegra_pll_x_out0 = {
 
 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
        /* PLLE special case: use cpcon field to store cml divider value */
-       { 12000000,  100000000, 200, 1,  24, 13},
+       { 12000000,  100000000, 150, 1,  18, 11},
        { 216000000, 100000000, 200, 18, 24, 13},
 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
        { 13000000,  100000000, 200, 1,  26, 13},