ARM: tegra: clock: Set Tegra3 LPDDR2 minimum rate to 25MHz
Alex Frid [Fri, 15 Jul 2011 04:35:48 +0000 (21:35 -0700)]
Original-Change-Id: I8cd5cfef8a040ffa5f0959b5a294b25a21fcfa8b
Reviewed-on: http://git-master/r/41141
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: R47886089e5b3b73c58372645ec7ea282a0cfa698

arch/arm/mach-tegra/tegra3_clocks.c
arch/arm/mach-tegra/tegra3_emc.c

index 77e3542..7f63000 100644 (file)
@@ -3788,7 +3788,7 @@ static struct clk tegra_clk_emc = {
        .ops = &tegra_emc_clk_ops,
        .reg = 0x19c,
        .max_rate = 800000000,
-       .min_rate = 50000000,
+       .min_rate = 25000000,
        .inputs = mux_pllm_pllc_pllp_clkm,
        .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
        .u.periph = {
index 44a7009..3a7e64e 100644 (file)
@@ -43,6 +43,7 @@ static bool emc_enable;
 #endif
 module_param(emc_enable, bool, 0644);
 
+#define EMC_MIN_RATE_DDR3              50000000
 #define EMC_STATUS_UPDATE_TIMEOUT      100
 #define TEGRA_EMC_TABLE_MAX_SIZE       16
 
@@ -847,6 +848,9 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size)
                pr_err("Not supported DRAM type %u\n", dram_type);
                return;
        }
+       if (dram_type == DRAM_TYPE_DDR3)
+               emc->min_rate = EMC_MIN_RATE_DDR3;
+
        reg = emc_readl(EMC_CFG_2) & (~EMC_CFG_2_MODE_MASK);
        reg |= ((dram_type == DRAM_TYPE_LPDDR2) ? EMC_CFG_2_PD_MODE :
                EMC_CFG_2_SREF_MODE) << EMC_CFG_2_MODE_SHIFT;