arm: tegra: sdhci: Limit eMMC,SDIO,SD DDR clock
Pavan Kunapuli [Wed, 9 May 2012 13:29:19 +0000 (18:29 +0530)]
Limit eMMC, SD and SDIO DDR mode clock to 41MHz.

Bug 967719

Change-Id: Iaccc5b771b81b15226f87684b547ad1fb7dd38d3
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/101173
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

arch/arm/mach-tegra/board-cardhu-sdhci.c
arch/arm/mach-tegra/board-enterprise-sdhci.c
arch/arm/mach-tegra/board-kai-sdhci.c

index e203e6c..c4e631d 100644 (file)
@@ -153,6 +153,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
        .wp_gpio = -1,
        .power_gpio = -1,
        .tap_delay = 0x0F,
+       .ddr_clk_limit = 41000000,
 /*     .is_voltage_switch_supported = false,
        .vdd_rail_name = NULL,
        .slot_rail_name = NULL,
@@ -167,6 +168,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
        .wp_gpio = CARDHU_SD_WP,
        .power_gpio = -1,
        .tap_delay = 0x0F,
+       .ddr_clk_limit = 41000000,
 /*     .is_voltage_switch_supported = true,
        .vdd_rail_name = "vddio_sdmmc1",
        .slot_rail_name = "vddio_sd_slot",
@@ -182,11 +184,11 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
        .power_gpio = -1,
        .is_8bit = 1,
        .tap_delay = 0x0F,
+       .ddr_clk_limit = 41000000,
        .mmc_data = {
                .built_in = 1,
        }
-/*     .tap_delay = 6,
-       .is_voltage_switch_supported = false,
+/*     .is_voltage_switch_supported = false,
        .vdd_rail_name = NULL,
        .slot_rail_name = NULL,
        .vdd_max_uv = -1,
index 2390bf6..4e96908 100644 (file)
@@ -145,6 +145,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
        .power_gpio = -1,
        .tap_delay = 0x0F,
        .max_clk_limit = 45000000,
+       .ddr_clk_limit = 41000000,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
@@ -152,6 +153,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
        .wp_gpio = -1,
        .power_gpio = -1,
        .tap_delay = 0x0F,
+       .ddr_clk_limit = 41000000,
 };
 
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
@@ -160,6 +162,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
        .power_gpio = -1,
        .is_8bit = 1,
        .tap_delay = 0x0F,
+       .ddr_clk_limit = 41000000,
        .mmc_data = {
                .built_in = 1,
        }
index 7cab478..8d1d4a9 100644 (file)
@@ -114,6 +114,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
        .wp_gpio = -1,
        .power_gpio = -1,
        .tap_delay = 0x0F,
+       .ddr_clk_limit = 41000000,
 /*     .is_voltage_switch_supported = false,
        .vdd_rail_name = NULL,
        .slot_rail_name = NULL,
@@ -129,6 +130,7 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
        .wp_gpio = -1,
        .power_gpio = -1,
        .tap_delay = 0x0F,
+       .ddr_clk_limit = 41000000,
 /*     .is_voltage_switch_supported = true,
        .vdd_rail_name = "vddio_sdmmc1",
        .slot_rail_name = "vddio_sd_slot",
@@ -144,11 +146,11 @@ static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
        .power_gpio = -1,
        .is_8bit = 1,
        .tap_delay = 0x0F,
+       .ddr_clk_limit = 41000000,
        .mmc_data = {
                .built_in = 1,
        }
-/*     .tap_delay = 6,
-       .is_voltage_switch_supported = false,
+/*     .is_voltage_switch_supported = false,
        .vdd_rail_name = NULL,
        .slot_rail_name = NULL,
        .vdd_max_uv = -1,