Revert "Revert "ARM: tegra: whistler: Add AP25 EMC scaling table""
Prashant Gaikwad [Fri, 18 Nov 2011 09:10:34 +0000 (14:10 +0530)]
This reverts commit 5f1a3978ce2f00d531d4c831b7b34ed55e960572.

Change-Id: I6650d3e51eb5fcb4048e8ed84bdafebc0307ce5a
Reviewed-on: http://git-master/r/72930
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

arch/arm/mach-tegra/board-whistler-memory.c

index 918e96d..d425311 100644 (file)
@@ -281,7 +281,7 @@ static const struct tegra_emc_table whistler_emc_tables_elpida_300Mhz[] = {
        }
 };
 
-static const struct tegra_emc_table whistler_emc_tables_elpida_400Mhz[] = {
+static const struct tegra_emc_table whistler_emc_tables_elpida_380Mhz[] = {
        {
                .rate = 23750,   /* SDRAM frquency */
                .regs = {
@@ -317,11 +317,11 @@ static const struct tegra_emc_table whistler_emc_tables_elpida_400Mhz[] = {
                        0x00000008,   /* TCLKSTABLE */
                        0x00000002,   /* TCLKSTOP */
                        0x00000060,   /* TREFBW */
-                       0x00000004,   /* QUSE_EXTRA */
+                       0x00000000,   /* QUSE_EXTRA */
                        0x00000003,   /* FBIO_CFG6 */
                        0x00000000,   /* ODT_WRITE */
                        0x00000000,   /* ODT_READ */
-                       0x00000082,   /* FBIO_CFG5 */
+                       0x00000282,   /* FBIO_CFG5 */
                        0xa0ae04ae,   /* CFG_DIG_DLL */
                        0x0001f800,   /* DLL_XFORM_DQS */
                        0x00000000,   /* DLL_XFORM_QUSE */
@@ -334,7 +334,7 @@ static const struct tegra_emc_table whistler_emc_tables_elpida_400Mhz[] = {
                }
        },
        {
-               .rate = 63333,   /* SDRAM frquency */
+               .rate = 63334,   /* SDRAM frquency */
                .regs = {
                        0x00000004,   /* RC */
                        0x00000009,   /* RFC */
@@ -368,11 +368,11 @@ static const struct tegra_emc_table whistler_emc_tables_elpida_400Mhz[] = {
                        0x00000008,   /* TCLKSTABLE */
                        0x00000002,   /* TCLKSTOP */
                        0x00000107,   /* TREFBW */
-                       0x00000005,   /* QUSE_EXTRA */
+                       0x00000000,   /* QUSE_EXTRA */
                        0x00000000,   /* FBIO_CFG6 */
                        0x00000000,   /* ODT_WRITE */
                        0x00000000,   /* ODT_READ */
-                       0x00000082,   /* FBIO_CFG5 */
+                       0x00000282,   /* FBIO_CFG5 */
                        0xa0ae04ae,   /* CFG_DIG_DLL */
                        0x0001f800,   /* DLL_XFORM_DQS */
                        0x00000000,   /* DLL_XFORM_QUSE */
@@ -419,11 +419,11 @@ static const struct tegra_emc_table whistler_emc_tables_elpida_400Mhz[] = {
                        0x00000008,   /* TCLKSTABLE */
                        0x00000002,   /* TCLKSTOP */
                        0x0000018c,   /* TREFBW */
-                       0x00000005,   /* QUSE_EXTRA */
+                       0x00000000,   /* QUSE_EXTRA */
                        0x00000001,   /* FBIO_CFG6 */
                        0x00000000,   /* ODT_WRITE */
                        0x00000000,   /* ODT_READ */
-                       0x00000082,   /* FBIO_CFG5 */
+                       0x00000282,   /* FBIO_CFG5 */
                        0xa0ae04ae,   /* CFG_DIG_DLL */
                        0x0001f000,   /* DLL_XFORM_DQS */
                        0x00000000,   /* DLL_XFORM_QUSE */
@@ -470,11 +470,11 @@ static const struct tegra_emc_table whistler_emc_tables_elpida_400Mhz[] = {
                        0x00000008,   /* TCLKSTABLE */
                        0x00000002,   /* TCLKSTOP */
                        0x00000317,   /* TREFBW */
-                       0x00000005,   /* QUSE_EXTRA */
+                       0x00000000,   /* QUSE_EXTRA */
                        0x00000002,   /* FBIO_CFG6 */
                        0x00000000,   /* ODT_WRITE */
                        0x00000000,   /* ODT_READ */
-                       0x00000082,   /* FBIO_CFG5 */
+                       0x00000282,   /* FBIO_CFG5 */
                        0xa06204ae,   /* CFG_DIG_DLL */
                        0x007f7010,   /* DLL_XFORM_DQS */
                        0x00000000,   /* DLL_XFORM_QUSE */
@@ -487,6 +487,57 @@ static const struct tegra_emc_table whistler_emc_tables_elpida_400Mhz[] = {
                }
        },
        {
+               .rate = 300000,   /* SDRAM frquency */
+               .regs = {
+                       0x00000012,   /* RC */
+                       0x00000027,   /* RFC */
+                       0x0000000d,   /* RAS */
+                       0x00000006,   /* RP */
+                       0x00000007,   /* R2W */
+                       0x00000005,   /* W2R */
+                       0x00000003,   /* R2P */
+                       0x0000000b,   /* W2P */
+                       0x00000006,   /* RD_RCD */
+                       0x00000006,   /* WR_RCD */
+                       0x00000003,   /* RRD */
+                       0x00000003,   /* REXT */
+                       0x00000003,   /* WDV */
+                       0x00000007,   /* QUSE */
+                       0x00000004,   /* QRST */
+                       0x00000009,   /* QSAFE */
+                       0x0000000d,   /* RDV */
+                       0x0000045f,   /* REFRESH */
+                       0x00000000,   /* BURST_REFRESH_NUM */
+                       0x00000004,   /* PDEX2WR */
+                       0x00000004,   /* PDEX2RD */
+                       0x00000006,   /* PCHG2PDEN */
+                       0x00000008,   /* ACT2PDEN */
+                       0x00000001,   /* AR2PDEN */
+                       0x0000000f,   /* RW2PDEN */
+                       0x0000002a,   /* TXSR */
+                       0x00000003,   /* TCKE */
+                       0x0000000f,   /* TFAW */
+                       0x00000007,   /* TRPAB */
+                       0x00000007,   /* TCLKSTABLE */
+                       0x00000002,   /* TCLKSTOP */
+                       0x000004e0,   /* TREFBW */
+                       0x00000006,   /* QUSE_EXTRA */
+                       0x00000002,   /* FBIO_CFG6 */
+                       0x00000000,   /* ODT_WRITE */
+                       0x00000000,   /* ODT_READ */
+                       0x00000282,   /* FBIO_CFG5 */
+                       0xe05e048b,   /* CFG_DIG_DLL */
+                       0x007f2010,   /* DLL_XFORM_DQS */
+                       0x00000000,   /* DLL_XFORM_QUSE */
+                       0x00000000,   /* ZCAL_REF_CNT */
+                       0x0000001b,   /* ZCAL_WAIT_CNT */
+                       0x00000000,   /* AUTO_CAL_INTERVAL */
+                       0x00000000,   /* CFG_CLKTRIM_0 */
+                       0x00000000,   /* CFG_CLKTRIM_1 */
+                       0x00000000,   /* CFG_CLKTRIM_2 */
+               }
+       },
+       {
                .rate = 380000,   /* SDRAM frquency */
                .regs = {
                        0x00000017,   /* RC */
@@ -558,6 +609,15 @@ static const struct tegra_emc_chip whistler_emc_chips[] = {
                .table = whistler_emc_tables_elpida_300Mhz,
                .table_size = ARRAY_SIZE(whistler_emc_tables_elpida_300Mhz)
        },
+       {
+               .description = "Elpida 380MHz",
+               .mem_manufacturer_id = 0x0303,
+               .mem_revision_id1 = 0x0101,
+               .mem_revision_id2 = 0,
+               .mem_pid = 0x5454,
+               .table = whistler_emc_tables_elpida_380Mhz,
+               .table_size = ARRAY_SIZE(whistler_emc_tables_elpida_380Mhz)
+       },
 };
 
 int __init whistler_emc_init(void)