ARM: Tegra: Roth: Update Memory Config
Matt Wagner [Fri, 15 Feb 2013 02:10:11 +0000 (18:10 -0800)]
Change VTTGEN controls and add 900Mhz

Bug 1181038

Change-Id: Ie5a98c25cea6e0906f90cdde4413c4c2030bcf1b
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-on: http://git-master/r/200990
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit

arch/arm/mach-tegra/board-roth-memory.c

index 4cc605e..e99f3d8 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 NVIDIA, Inc.
+ * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -104,7 +104,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = {
                        0x77ffc084, /* EMC_XM2CLKPADCTRL */
                        0x81f1f108, /* EMC_XM2COMPPADCTRL */
                        0x03035504, /* EMC_XM2VTTGENPADCTRL */
-                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
                        0x0000003f, /* EMC_DSR_VTTGEN_DRV */
                        0x00000000, /* EMC_TXDSRVTTGEN */
                        0x02000000, /* EMC_FBIO_SPARE */
@@ -300,7 +300,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = {
                        0x77ffc084, /* EMC_XM2CLKPADCTRL */
                        0x81f1f108, /* EMC_XM2COMPPADCTRL */
                        0x03035504, /* EMC_XM2VTTGENPADCTRL */
-                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
                        0x0000003f, /* EMC_DSR_VTTGEN_DRV */
                        0x00000000, /* EMC_TXDSRVTTGEN */
                        0x02000000, /* EMC_FBIO_SPARE */
@@ -496,7 +496,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = {
                        0x77ffc084, /* EMC_XM2CLKPADCTRL */
                        0x81f1f108, /* EMC_XM2COMPPADCTRL */
                        0x03035504, /* EMC_XM2VTTGENPADCTRL */
-                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
                        0x0000003f, /* EMC_DSR_VTTGEN_DRV */
                        0x00000000, /* EMC_TXDSRVTTGEN */
                        0x02000000, /* EMC_FBIO_SPARE */
@@ -692,7 +692,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = {
                        0x77ffc084, /* EMC_XM2CLKPADCTRL */
                        0x81f1f108, /* EMC_XM2COMPPADCTRL */
                        0x03035504, /* EMC_XM2VTTGENPADCTRL */
-                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
                        0x0000003f, /* EMC_DSR_VTTGEN_DRV */
                        0x00000000, /* EMC_TXDSRVTTGEN */
                        0x02000000, /* EMC_FBIO_SPARE */
@@ -888,7 +888,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = {
                        0x77ffc084, /* EMC_XM2CLKPADCTRL */
                        0x81f1f108, /* EMC_XM2COMPPADCTRL */
                        0x03035504, /* EMC_XM2VTTGENPADCTRL */
-                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
                        0x0000003f, /* EMC_DSR_VTTGEN_DRV */
                        0x00000000, /* EMC_TXDSRVTTGEN */
                        0x02000000, /* EMC_FBIO_SPARE */
@@ -1084,7 +1084,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = {
                        0x77ffc084, /* EMC_XM2CLKPADCTRL */
                        0x81f1f108, /* EMC_XM2COMPPADCTRL */
                        0x03035504, /* EMC_XM2VTTGENPADCTRL */
-                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
                        0x0000003f, /* EMC_DSR_VTTGEN_DRV */
                        0x00000000, /* EMC_TXDSRVTTGEN */
                        0x02000000, /* EMC_FBIO_SPARE */
@@ -1993,7 +1993,7 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = {
                0x41,       /* Rev 4.0.3 */
                624000,     /* SDRAM frequency */
                1100,       /* min voltage */
-               "pll_c",    /* clock source id */
+               "pll_m",    /* clock source id */
                0x20000000, /* CLK_SOURCE_EMC */
                99,         /* number of burst_regs */
                30,         /* number of trim_regs (each channel) */
@@ -2381,6 +2381,202 @@ static struct tegra11_emc_table p2454_h5tc4g63afr_pba_table[] = {
                0x00000000, /* Mode Register 4 */
                1200,       /* expected dvfs latency (ns) */
        },
+       {
+               0x41,       /* Rev 4.0.3 */
+               900000,     /* SDRAM frequency */
+               1250,       /* min voltage */
+               "pll_m",    /* clock source id */
+               0x80000000, /* CLK_SOURCE_EMC */
+               99,         /* number of burst_regs */
+               30,         /* number of trim_regs (each channel) */
+               11,         /* number of up_down_regs */
+               {
+                       0x0000002b, /* EMC_RC */
+                       0x000000f1, /* EMC_RFC */
+                       0x00000000, /* EMC_RFC_SLR */
+                       0x0000001e, /* EMC_RAS */
+                       0x0000000b, /* EMC_RP */
+                       0x00000009, /* EMC_R2W */
+                       0x0000000f, /* EMC_W2R */
+                       0x00000005, /* EMC_R2P */
+                       0x00000018, /* EMC_W2P */
+                       0x0000000b, /* EMC_RD_RCD */
+                       0x0000000b, /* EMC_WR_RCD */
+                       0x00000004, /* EMC_RRD */
+                       0x00000001, /* EMC_REXT */
+                       0x00000000, /* EMC_WEXT */
+                       0x00000007, /* EMC_WDV */
+                       0x00000007, /* EMC_WDV_MASK */
+                       0x0000000d, /* EMC_IBDLY */
+                       0x000f000c, /* EMC_PUTERM_EXTRA */
+                       0x00000000, /* EMC_CDB_CNTL_2 */
+                       0x0000000a, /* EMC_QRST */
+                       0x00000016, /* EMC_RDV_MASK */
+                       0x00001c39, /* EMC_REFRESH */
+                       0x00000000, /* EMC_BURST_REFRESH_NUM */
+                       0x0000070e, /* EMC_PRE_REFRESH_REQ_CNT */
+                       0x00000004, /* EMC_PDEX2WR */
+                       0x00000015, /* EMC_PDEX2RD */
+                       0x00000001, /* EMC_PCHG2PDEN */
+                       0x00000000, /* EMC_ACT2PDEN */
+                       0x000000e8, /* EMC_AR2PDEN */
+                       0x0000001d, /* EMC_RW2PDEN */
+                       0x000000fd, /* EMC_TXSR */
+                       0x00000200, /* EMC_TXSRDLL */
+                       0x00000006, /* EMC_TCKE */
+                       0x00000006, /* EMC_TCKESR */
+                       0x00000006, /* EMC_TPD */
+                       0x00000026, /* EMC_TFAW */
+                       0x00000000, /* EMC_TRPAB */
+                       0x00000009, /* EMC_TCLKSTABLE */
+                       0x0000000a, /* EMC_TCLKSTOP */
+                       0x00001c7a, /* EMC_TREFBW */
+                       0x00000000, /* EMC_QUSE_EXTRA */
+                       0x80000020, /* EMC_ODT_WRITE */
+                       0x00000000, /* EMC_ODT_READ */
+                       0x00005088, /* EMC_FBIO_CFG5 */
+                       0xf0030191, /* EMC_CFG_DIG_DLL */
+                       0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+                       0x00000008, /* EMC_DLL_XFORM_DQS4 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS5 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS6 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS7 */
+                       0x00028007, /* EMC_DLL_XFORM_QUSE4 */
+                       0x00028007, /* EMC_DLL_XFORM_QUSE5 */
+                       0x00028007, /* EMC_DLL_XFORM_QUSE6 */
+                       0x00028007, /* EMC_DLL_XFORM_QUSE7 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+                       0x001112a0, /* EMC_XM2CMDPADCTRL */
+                       0x00000000, /* EMC_XM2CMDPADCTRL4 */
+                       0x0000013d, /* EMC_XM2DQSPADCTRL2 */
+                       0x00000000, /* EMC_XM2DQPADCTRL2 */
+                       0x77ffc085, /* EMC_XM2CLKPADCTRL */
+                       0x81f1f508, /* EMC_XM2COMPPADCTRL */
+                       0x07077504, /* EMC_XM2VTTGENPADCTRL */
+                       0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+                       0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+                       0x00000000, /* EMC_TXDSRVTTGEN */
+                       0x02000000, /* EMC_FBIO_SPARE */
+                       0x00000801, /* EMC_CTT_TERM_CTRL */
+                       0x00020000, /* EMC_ZCAL_INTERVAL */
+                       0x00000120, /* EMC_ZCAL_WAIT_CNT */
+                       0x00cb000f, /* EMC_MRS_WAIT_CNT */
+                       0x00cb000f, /* EMC_MRS_WAIT_CNT2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+                       0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+                       0x00000004, /* EMC_CTT */
+                       0x00000004, /* EMC_CTT_DURATION */
+                       0x8000388a, /* EMC_DYN_SELF_REF_CONTROL */
+                       0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */
+                       0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */
+                       0x0000000e, /* MC_EMEM_ARB_CFG */
+                       0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+                       0x00000005, /* MC_EMEM_ARB_TIMING_RCD */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_RP */
+                       0x00000016, /* MC_EMEM_ARB_TIMING_RC */
+                       0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */
+                       0x00000012, /* MC_EMEM_ARB_TIMING_FAW */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+                       0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+                       0x0000000f, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+                       0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+                       0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
+                       0x00000009, /* MC_EMEM_ARB_TIMING_W2R */
+                       0x09060202, /* MC_EMEM_ARB_DA_TURNS */
+                       0x001b1016, /* MC_EMEM_ARB_DA_COVERS */
+                       0x734f2b17, /* MC_EMEM_ARB_MISC0 */
+                       0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x0000000c, /* EMC_QUSE */
+                       0x0000000a, /* EMC_EINPUT */
+                       0x00000006, /* EMC_EINPUT_DURATION */
+                       0x00000008, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000d, /* EMC_QSAFE */
+                       0x00028007, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000016, /* EMC_RDV */
+                       0x00249249, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x00004008, /* EMC_DLL_XFORM_DQ0 */
+                       0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000f0f, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS1 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS2 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS3 */
+                       0x00004008, /* EMC_DLL_XFORM_DQ1 */
+                       0x00004008, /* EMC_DLL_XFORM_DQ2 */
+                       0x00004008, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00028007, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00028007, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00028007, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x00000000, /* EMC_CDB_CNTL_1 */
+                       0x00000006, /* EMC_FBIO_CFG6 */
+                       0x0000000c, /* EMC_QUSE */
+                       0x0000000a, /* EMC_EINPUT */
+                       0x00000006, /* EMC_EINPUT_DURATION */
+                       0x00000008, /* EMC_DLL_XFORM_DQS0 */
+                       0x0000000d, /* EMC_QSAFE */
+                       0x00028007, /* EMC_DLL_XFORM_QUSE0 */
+                       0x00000016, /* EMC_RDV */
+                       0x00249249, /* EMC_XM2DQSPADCTRL4 */
+                       0x10410400, /* EMC_XM2DQSPADCTRL3 */
+                       0x00004008, /* EMC_DLL_XFORM_DQ0 */
+                       0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+                       0x00000b0b, /* EMC_XM2CLKPADCTRL2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+                       0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS1 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS2 */
+                       0x00000008, /* EMC_DLL_XFORM_DQS3 */
+                       0x00004008, /* EMC_DLL_XFORM_DQ1 */
+                       0x00004008, /* EMC_DLL_XFORM_DQ2 */
+                       0x00004008, /* EMC_DLL_XFORM_DQ3 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+                       0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+                       0x00028007, /* EMC_DLL_XFORM_QUSE1 */
+                       0x00028007, /* EMC_DLL_XFORM_QUSE2 */
+                       0x00028007, /* EMC_DLL_XFORM_QUSE3 */
+               },
+               {
+                       0x000001cd, /* MC_PTSA_GRANT_DECREMENT */
+                       0x00080008, /* MC_LATENCY_ALLOWANCE_G2_0 */
+                       0x00080008, /* MC_LATENCY_ALLOWANCE_G2_1 */
+                       0x0009000a, /* MC_LATENCY_ALLOWANCE_NV_0 */
+                       0x0000000a, /* MC_LATENCY_ALLOWANCE_NV2_0 */
+                       0x000a000a, /* MC_LATENCY_ALLOWANCE_NV_2 */
+                       0x000e000a, /* MC_LATENCY_ALLOWANCE_NV_1 */
+                       0x0000000e, /* MC_LATENCY_ALLOWANCE_NV2_1 */
+                       0x000e000e, /* MC_LATENCY_ALLOWANCE_NV3 */
+                       0x0060002d, /* MC_LATENCY_ALLOWANCE_EPP_0 */
+                       0x00600060, /* MC_LATENCY_ALLOWANCE_EPP_1 */
+               },
+               0x0000004d, /* EMC_ZCAL_WAIT_CNT after clock change */
+               0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+               0x53000000, /* EMC_CFG */
+               0x80000115, /* Mode Register 0 */
+               0x80100002, /* Mode Register 1 */
+               0x80200420, /* Mode Register 2 */
+               0x00000000, /* Mode Register 4 */
+               1200,       /* expected dvfs latency (ns) */
+       },
 };
 
 static struct tegra11_emc_pdata p2454_h5tc4g63afr_pba_pdata = {