ARM: tegra: clock: Add CEC clock
Ankit Pashiney [Wed, 20 Jun 2012 03:06:43 +0000 (20:06 -0700)]
Added CEC clock for tegra3

bug 894195

Change-Id: I7882371f3ab0f03454d372a7240acd9bd78c2c9c
Signed-off-by: Ankit Pashiney <apashiney@nvidia.com>
Reviewed-on: http://git-master/r/105518
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

arch/arm/mach-tegra/tegra30_clocks.c

index 9e3668e..2a7e324 100644 (file)
@@ -4249,6 +4249,7 @@ struct clk tegra_list_clks[] = {
        PERIPH_CLK("vcp",       "tegra-avp",            "vcp",  29,     0,      250000000, mux_clk_m,                   0),
        PERIPH_CLK("bsea",      "tegra-avp",            "bsea", 62,     0,      250000000, mux_clk_m,                   0),
        PERIPH_CLK("bsev",      "tegra-aes",            "bsev", 63,     0,      250000000, mux_clk_m,                   0),
+       PERIPH_CLK("cec",       "tegra_cec",            NULL,   136,    0,      26000000,  mux_clk_m,                   PERIPH_ON_APB),
        PERIPH_CLK("vde",       "vde",                  NULL,   61,     0x1c8,  600000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_INT),
        PERIPH_CLK("csite",     "csite",                NULL,   73,     0x1d4,  144000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71), /* max rate ??? */
        PERIPH_CLK("la",        "la",                   NULL,   76,     0x1f8,  26000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),