ARM: tegra: usb_phy: Remove WAR for HSIC bus reset
srinivas [Wed, 29 Aug 2012 17:24:45 +0000 (22:24 +0530)]
When UHSIC_DISABLE_BUSRESET, UHSIC_FORCE_XCVR_MODE
bits are set, controller forces bus reset using the
WAR sequences in T30. As HSIC bus reset timer issue
is fixed in T114, these settings can be removed.

Bug 1021578

Change-Id: I21e5acc533d1bec5691d7142eb6776e852db9392
Signed-off-by: srinivas thaduvai <sthaduvai@nvidia.com>
Reviewed-on: http://git-master/r/130474
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

arch/arm/mach-tegra/tegra11x_usb_phy.c

index d137e86..89ac2f5 100644 (file)
@@ -2128,8 +2128,6 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
 
        val = readl(base + UHSIC_MISC_CFG0);
        val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
-       /* Disable generic bus reset, to allow AP30 specific bus reset*/
-       val |= UHSIC_DISABLE_BUSRESET;
        writel(val, base + UHSIC_MISC_CFG0);
 
        val = readl(base + UHSIC_MISC_CFG1);
@@ -2262,15 +2260,6 @@ static int uhsic_phy_bus_port_power(struct tegra_usb_phy *phy)
        val |= UHSIC_DETECT_SHORT_CONNECT;
        writel(val, base + UHSIC_MISC_CFG0);
        udelay(1);
-
-       val = readl(base + UHSIC_MISC_CFG0);
-       val |= UHSIC_FORCE_XCVR_MODE;
-       writel(val, base + UHSIC_MISC_CFG0);
-
-       val = readl(base + UHSIC_PADS_CFG1);
-       val &= ~UHSIC_RPD_STROBE;
-       writel(val, base + UHSIC_PADS_CFG1);
-
        if (phy->pdata->ops && phy->pdata->ops->port_power)
                phy->pdata->ops->port_power();