arm: tegra: macallan: set the LDO5 to 2.8V
authorHunk Lin <hulin@nvidia.com>
Sat, 11 May 2013 07:47:36 +0000 (15:47 +0800)
committerHarshada Kale <hkale@nvidia.com>
Mon, 13 May 2013 10:25:06 +0000 (03:25 -0700)
commitff221e553ea99b822181965b1ae5fc8191b72996
tree90df36522354171529679311c270479ad571567c
parentc1bbae15f0eb8681419ef182f055ebd6b9663d05
arm: tegra: macallan: set the LDO5 to 2.8V

This rail is used for avdd of CAM2. Checked the datasheet of OV9772,
the avdd's typical value is 2.8V.

Bug 1287854

Change-Id: I9d38554f79d02cf1177c4a44c77b8b14d371e08a
Signed-off-by: Hunk Lin <hulin@nvidia.com>
Reviewed-on: http://git-master/r/227723
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-by: Hayden Du <haydend@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
arch/arm/mach-tegra/board-macallan-power.c