ARM: tegra11: power: Set safe cold voltage in DFLL mode
authorAlex Frid <afrid@nvidia.com>
Thu, 31 Jan 2013 22:52:01 +0000 (14:52 -0800)
committerMandar Padmawar <mpadmawar@nvidia.com>
Tue, 5 Feb 2013 14:59:17 +0000 (06:59 -0800)
commitfea89035708cc9f21f995194cb1586672e9c0e05
treea36ef3457b827d987e839cd2f530acf8eb51aa69
parentd049c47291b9a94f2b72fc64a40559cc37c0498a
ARM: tegra11: power: Set safe cold voltage in DFLL mode

Used regulator API to set CPU voltage at cold temperature minimum
limit if DFLL is selected as fast G CPU clock source, and

- CPU is switching to LP cluster
- on entry to system suspend

This is done since in both cases: suspend and LP cluster operations,
CPU rail is off while temperature may go down, and on exit from each
state CPU will be running on DFLL clock for some time before CL-DVFS
regulation starts.

Change-Id: I02e06a2e92f348a147693ad2b811d7bedb4e70e2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/196289
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
arch/arm/mach-tegra/dvfs.c
arch/arm/mach-tegra/dvfs.h
arch/arm/mach-tegra/tegra11_clocks.c
arch/arm/mach-tegra/tegra_cl_dvfs.c