sparc64: Fix MSIQ HV call ordering in pci_sun4v_msiq_build_irq().
authorDavid S. Miller <davem@davemloft.net>
Thu, 22 Dec 2011 21:23:59 +0000 (13:23 -0800)
committerRohan Somvanshi <rsomvanshi@nvidia.com>
Wed, 11 Jan 2012 18:16:51 +0000 (10:16 -0800)
commitfadd5e5a07db923cbee627df77f77aac8106153d
tree64692a291ba5bf2bd2b4e7680c42a9a3f744baa5
parent3ea9240885fc8a78d3066df9e4eca4e192ef1c2d
sparc64: Fix MSIQ HV call ordering in pci_sun4v_msiq_build_irq().

[ Upstream commit 7cc8583372a21d98a23b703ad96cab03180b5030 ]

This silently was working for many years and stopped working on
Niagara-T3 machines.

We need to set the MSIQ to VALID before we can set it's state to IDLE.

On Niagara-T3, setting the state to IDLE first was causing HV_EINVAL
errors.  The hypervisor documentation says, rather ambiguously, that
the MSIQ must be "initialized" before one can set the state.

I previously understood this to mean merely that a successful setconf()
operation has been performed on the MSIQ, which we have done at this
point.  But it seems to also mean that it has been set VALID too.

Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Change-Id: I6c1c9cf6f1336fc332d2e1fc0453e2bc16a7089b
Reviewed-on: http://git-master/r/74204
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
arch/sparc/kernel/pci_sun4v.c