ARM: tegra: Dalmore: Set SDMMC1,3 clock to 156 MHZ
authorNaveen Kumar Arepalli <naveenk@nvidia.com>
Fri, 24 May 2013 06:05:13 +0000 (11:05 +0530)
committerRiham Haidar <rhaidar@nvidia.com>
Wed, 29 May 2013 18:57:10 +0000 (11:57 -0700)
commitfa015e65bd72939e9e9d9bf57273e383255d5697
treea22017b3db119494bb04bb4a28955da8270dee4c
parent7e72685b51d1e4e11c1379b8b9404b51ae412d2e
ARM: tegra: Dalmore: Set SDMMC1,3 clock to 156 MHZ

1. Adding vdd_core regulators for sdmmc3 to be used for
setting core voltage constraints during frequency tuning.

2. Setting SD and SDIO max clock to 156MHz on Dalmore A05
board.

Bug 1238045

Change-Id: I1ba0cf8e434680bc09877156b1066c5eb06dcf24
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/222461
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
arch/arm/mach-tegra/board-dalmore-power.c
arch/arm/mach-tegra/board-dalmore-sdhci.c