ARM: 7091/1: errata: D-cache line maintenance operation by MVA may not succeed
authorWill Deacon <will.deacon@arm.com>
Thu, 15 Sep 2011 10:45:15 +0000 (11:45 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Sat, 17 Sep 2011 11:47:17 +0000 (12:47 +0100)
commitf630c1bdfbf8fe423325beaf60027cfc7fd7c610
tree9091179ae505fcb5aff937315c4f9c96602cba9a
parent279b1e0fd90ef63c7acb34a5ca573f065a6fefb4
ARM: 7091/1: errata: D-cache line maintenance operation by MVA may not succeed

This patch implements a workaround for erratum 764369 affecting
Cortex-A9 MPCore with two or more processors (all current revisions).
Under certain timing circumstances, a data cache line maintenance
operation by MVA targeting an Inner Shareable memory region may fail to
proceed up to either the Point of Coherency or to the Point of
Unification of the system. This workaround adds a DSB instruction before
the relevant cache maintenance functions and sets a specific bit in the
diagnostic control register of the SCU.

Cc: <stable@kernel.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/Kconfig
arch/arm/kernel/smp_scu.c
arch/arm/mm/cache-v7.S