ARM: tegra: dvfs: Update SCLK dvfs table
authorAlex Frid <afrid@nvidia.com>
Fri, 11 Feb 2011 10:15:29 +0000 (02:15 -0800)
committerDan Willemsen <dwillemsen@nvidia.com>
Thu, 1 Dec 2011 05:41:57 +0000 (21:41 -0800)
commitf3162c3f241b9228a9f3d2757609b9859d47e694
tree8a525547db9483b8f541ff5ebe4add5aedb7347b
parentdc55cb3495e0f5437e339c6401dc2c8ce4c627c7
ARM: tegra: dvfs: Update SCLK dvfs table

Updated system bus clock dvfs table with recent characterization
data. As a result nominal core voltage for SKUs with 240MHz SCLK
limit increased from 1.2V to 1.225V.

Original-Change-Id: I42a35f848bb0a410d393d930ddf1a87f86f25280
Reviewed-on: http://git-master/r/16272
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

Rebase-Id: Rda324012f2f1610da9480023d9fafc00ab9fdbd4
arch/arm/mach-tegra/tegra2_dvfs.c