perf_events: Add Intel Sandy Bridge offcore_response low-level support
authorStephane Eranian <eranian@google.com>
Mon, 6 Jun 2011 14:57:12 +0000 (16:57 +0200)
committerIngo Molnar <mingo@elte.hu>
Fri, 1 Jul 2011 09:06:37 +0000 (11:06 +0200)
commitee89cbc2d48150c7c0e9f2aaac00afde99af098c
tree8b690157409cab9fc1c887d7ea706b80e1d49e48
parentcd8a38d33e2528998998bae70a45ad27e442f114
perf_events: Add Intel Sandy Bridge offcore_response low-level support

This patch adds Intel Sandy Bridge offcore_response support by
providing the low-level constraint table for those events.

On Sandy Bridge, there are two offcore_response events. Each uses
its own dedictated extra register. But those registers are NOT shared
between sibling CPUs when HT is on unlike Nehalem/Westmere. They are
always private to each CPU. But they still need to be controlled within
an event group. All events within an event group must use the same
value for the extra MSR. That's not controlled by the second patch in
this series.

Furthermore on Sandy Bridge, the offcore_response events have NO
counter constraints contrary to what the official documentation
indicates, so drop the events from the contraint table.

Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/20110606145712.GA7304@quad
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/cpu/perf_event.c
arch/x86/kernel/cpu/perf_event_intel.c