arm: tegra: cardhu: move VI to PLL_P
authorJihoon Bang <jbang@nvidia.com>
Fri, 29 Jun 2012 20:54:34 +0000 (13:54 -0700)
committerRohan Somvanshi <rsomvanshi@nvidia.com>
Wed, 11 Jul 2012 13:41:09 +0000 (06:41 -0700)
commitec165877819d4b2077a3b96a070bab825a62d7cf
tree8b43805affbc8679144b6816d2900f0cd853f63c
parentdd4018153b7cee324bb2812c74109a4deb1ad796
arm: tegra: cardhu: move VI to PLL_P

As a part of effort to bring in 437MHz clock frequency in EMC,
We need to move VI from PLL_M to PLL_P.

Bug 1005576

Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/112704
(cherry picked from commit c175857e80355857b55e8eb2012c12e94e532835)

Change-Id: Icd314c01625f5c4765b0215735ceafb7d3f25d1e
Reviewed-on: http://git-master/r/114241
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
arch/arm/mach-tegra/board-cardhu.c