video: tegra: dc: power optimize DC and host1x clk
authorJon Mayo <jmayo@nvidia.com>
Tue, 17 Jul 2012 22:56:44 +0000 (15:56 -0700)
committerSimone Willett <swillett@nvidia.com>
Wed, 22 Aug 2012 22:01:41 +0000 (15:01 -0700)
commitced6edaf188e05194fc08b39ac0a89d1b56e94a5
treea0d11b7c8301e19b081fcc231b5e2432f355ab7f
parentea4da3a292039d772eba32b43048fe50e7f7377b
video: tegra: dc: power optimize DC and host1x clk

Use threaded IRQ to support enabling clocks in interrupt handling.
Use io_start and io_end to hold and release host1x clock.
Disable IRQ after it is first requested to balance enable/disable.
Use disable_irq_nosync() anywhere dc->lock is held to avoid deadlock.

Change tegra_dc_update_windows() to always be balanced with
tegra_dc_sync_windows(). Sync points (from host1x) are potentially lost if
clock gated after update, generally this only affects applications that
update at a slow frame rate.

To balance update and sync calls, Colormap/LUT code now performans a
sync_windows on a LUT change, this makes LUT changes slower and take effect
immediately.

Add a nosync version of tegra_dc_dsi_write_data to be used within dsi
module.

Bug 1031933
Bug 1002768
Bug 1036025
Bug 1013506
Bug 1025621
Bug 1028716
Bug 1029041
Bug 899059
Bug 887342
Bug 929609

Change-Id: I79454e265a96df66244275c2f3b0e4949f71bd02
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/123813
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
GVS: Gerrit_Virtual_Submit
drivers/video/tegra/dc/dc.c
drivers/video/tegra/dc/dc_priv.h
drivers/video/tegra/dc/dsi.c
drivers/video/tegra/dc/hdmi.c
drivers/video/tegra/dc/lut.c
drivers/video/tegra/dc/nvsd.c
drivers/video/tegra/dc/rgb.c
drivers/video/tegra/dc/window.c