video: tegra: dsi: fix DSI_PAD_CONTROL reg wr value on resume
authorBoris Suvorov <bsuvorov@nvidia.com>
Fri, 24 Feb 2012 21:22:28 +0000 (13:22 -0800)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 24 Mar 2012 00:32:18 +0000 (17:32 -0700)
commitc9320b28ee89fecfdbf9ad98ae5cac09183619f2
tree7feec87212d43cd1ee17c44854364822b9a0ddd0
parentb0d6789ec719bd59b2a27ceaac42e35b34573cc5
video: tegra: dsi: fix DSI_PAD_CONTROL reg wr value on resume

In panel resume path DSI_PAD_CONTROL value gets calibrated,
however later on values are overwritten with bit settings
for ulpm mode.

refactor value for reg write to only change ulpm related bits.

Change-Id: I9f9713bdf376c06b0e1b9f43b3e6c9f719bbd855
Signed-off-by: Boris Suvorov <bsuvorov@nvidia.com>
Reviewed-on: http://git-master/r/85873
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Rebase-Id: R192c61a086759bf4a5e76fec91907fbf3fa0756d
drivers/video/tegra/dc/dsi.c