ARM: tegra: dvfs: Update voltage recording in dfll mode
authorAlex Frid <afrid@nvidia.com>
Sun, 3 Feb 2013 06:17:19 +0000 (22:17 -0800)
committerMandar Padmawar <mpadmawar@nvidia.com>
Fri, 8 Feb 2013 16:16:26 +0000 (08:16 -0800)
commitb91a719567a57e96a628f9bb6dd5708070bf5b2a
tree61454622ac576ab7cdb13286cbe4ffaf923c6f7b
parent1b7d7b6c39d45a84135d66c7cf784dc4bbee788e
ARM: tegra: dvfs: Update voltage recording in dfll mode

In dfll mode rail voltage is adjusted automatically, but not exactly
to the expected level. When/if control is switched back from dfll h/w
cl-dvfs to s/w dvfs, false detection of matching voltage between new
target, and old dfll record is possible. To avoid this false detection
1mV was subtracted every time dfll voltage was recorded. After this
commit record is distorted by 1mV only once before the switch.

Change-Id: If3045293bda8c0240e2ce7fb3f1176288c9d150f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/196776
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>
arch/arm/mach-tegra/dvfs.c