media: video: fix clock settings for Tegra VI driver
authorBryan Wu <pengw@nvidia.com>
Wed, 4 Jun 2014 18:16:32 +0000 (11:16 -0700)
committerWinnie Hsu <whsu@nvidia.com>
Thu, 5 Jun 2014 01:08:43 +0000 (18:08 -0700)
commita7feb27765cf32d7da33659771fd0b2571c87b8d
treeea56dd7bcdf819fb9725d3ad733b9b931fd8dabe
parent141076cd925f093adff5971ae8970ae339007ae4
media: video: fix clock settings for Tegra VI driver

 - remove reduntant emc clock rate set which is controlled by DVFS
 - VI's maxim working clock freq is 300MHz
 - Change VI clock divider from an integer to a decimal, so the
   maxim VI clock on Cardhu should be 272MHz (PLL_P is 408MHz and
   divider is 1.5)

Bug 1478352

Change-Id: I4028ed8531d92300d131befb53a4c9dc9f90930d
Signed-off-by: Bryan Wu <pengw@nvidia.com>
Reviewed-on: http://git-master/r/419071
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Tested-by: Winnie Hsu <whsu@nvidia.com>
arch/arm/mach-tegra/tegra3_clocks.c
drivers/media/video/tegra_v4l2_camera.c