spi: tegra: register interrupt as ONESHOT
authorLaxman Dewangan <ldewangan@nvidia.com>
Mon, 14 May 2012 08:28:02 +0000 (13:28 +0530)
committerSimone Willett <swillett@nvidia.com>
Fri, 18 May 2012 20:45:03 +0000 (13:45 -0700)
commita763d40775269f8e29fea5780000014178eaf4b3
tree791f79739809c31012a7ec41c94eefd7ea9d1eaf
parent3fa0179bff425820a1c7aed0e55fac4f18f99658
spi: tegra: register interrupt as ONESHOT

The Tegra spi's engine is design as it generates interrupt
when any error occurs and it keep transferring data. It does
not stop the engine once error occurred and interrupt generated.
This may cause reentry of ISR as on error case, isr get called
where it clears interrupt and because it is still in progress,
it again interrupts and schedule the thread.
The second time scheduling of the isr/thread can cause the issue
in queue management and sw state.
So Making the interrupt as ONESHOT so that the interrupt will not
get schedule until the engine is reset in error case.

Change-Id: I96daaf50102aede93164c82b7f6da235d0a7fbfc
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/101547
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jui Chang Kuo <jckuo@nvidia.com>
Tested-by: Jui Chang Kuo <jckuo@nvidia.com>
drivers/spi/spi-tegra.c