ARM: cache-l2x0: fix L2 maintenance for R3P1_50
authorKirill Artamonov <kartamonov@nvidia.com>
Tue, 21 Aug 2012 12:02:22 +0000 (15:02 +0300)
committerSimone Willett <swillett@nvidia.com>
Tue, 28 Aug 2012 19:37:49 +0000 (12:37 -0700)
commita4e44614a5bae9e714ac99c43a6085194edb3c21
treea85f1e2b65db93a2859c263f29f01021a71ba94f
parent794066c1c027693fa4ae96b51fa9aa4f9a9ba002
ARM: cache-l2x0: fix L2 maintenance for R3P1_50

Do flush and clear by set/way instead of by-way by enabling
errata 727915 for pl310 revision R3P1_50.
By-way maintenance doesn't work with enabled lp2_in_idle on
Tegra3 platform using R3P1_50 revision of pl310.

Debug register access causes hang when
CONFIG_TRUSTED_FOUNDATIONS is defined. Don't access those
regeisters if CONFIG_TRUSTED_FOUNDATIONS is defined.

bug 983964

Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Change-Id: I76a3a9ef9dbcf86140ee26752202bf25542144e6
Reviewed-on: http://git-master/r/125153
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Tested-by: Antti Miettinen <amiettinen@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
arch/arm/include/asm/hardware/cache-l2x0.h
arch/arm/mm/cache-l2x0.c