ARM: tegra: clock: Auto-detect PLLP rate in uart init
authorAlex Frid <afrid@nvidia.com>
Fri, 13 Jan 2012 01:39:04 +0000 (17:39 -0800)
committerDan Willemsen <dwillemsen@nvidia.com>
Sat, 24 Mar 2012 02:57:46 +0000 (19:57 -0700)
commita2a02571730440b1cb2953e07f865087b310d276
tree53e517a12ac2ca2ff4e2c13e3ddecf9c7d6b98a8
parent96a95bbc4e2f26f4a639c52634725aabb9e1156c
ARM: tegra: clock: Auto-detect PLLP rate in uart init

Tegra3 platform may boot with one of the predefined fixed PLLP
(peripheral PLL) output rates: 216MHz, 408MHz, or 204MHz. This
commit implements auto-detection of PLLP rate, and debug uart
configuration during kernel uart initialization.

Bug 928260

Change-Id: I3fac4c462f28ac3dc1c72c0cc0f8f87fa0a809c4
Reviewed-on: http://git-master/r/75849
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/77294
Reviewed-by: Automatic_Commit_Validation_User

Rebase-Id: R1decd75752d7578b6b2715211188921605cbf97d
arch/arm/mach-tegra/board-cardhu.c