drm/i915: Set i9xx sdvo clock limits according to specifications
authorPatrik Jakobsson <patrik.r.jakobsson@gmail.com>
Wed, 13 Feb 2013 21:20:22 +0000 (22:20 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 28 Feb 2013 14:59:04 +0000 (06:59 -0800)
commita143ae690fbf24c2473d5c7c42875c29e150bd13
treed5db145f9d78d40feb5ba7fa5850fe1c17afb773
parent6bdf87562cb048e3e9a76d18e440794830647657
drm/i915: Set i9xx sdvo clock limits according to specifications

commit 4f7dfb6788dd022446847fbbfbe45e13bedb5be2 upstream.

The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
Since we do all calculations based on them being register values (which are
subtracted by 2) we need to specify them accordingly.

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56359
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/gpu/drm/i915/intel_display.c