ARM: tegra: t114: Mask UHS Modes for SDMMC1, SDMMC3
authorNaveen Kumar Arepalli <naveenk@nvidia.com>
Mon, 28 Jan 2013 17:03:00 +0000 (22:03 +0530)
committerRiham Haidar <rhaidar@nvidia.com>
Fri, 8 Feb 2013 00:38:49 +0000 (16:38 -0800)
commit9f6f9a18c28e31482e350866878a4ac8adc2a627
tree3d58dbf442a1bfd4f30a3af67c6bd6b05f99174f
parent21c1a7426737ed858ddc9ffa62e9963349a5415b
ARM: tegra: t114: Mask UHS Modes for SDMMC1, SDMMC3

Mask SDR104,DDR50,SDR50 modes for Dalmore(E1611)
Mask DDR 50 for ROTH.

Bug 1189241

Change-Id: I574315c2b557d9563a384db8f59c97bb0ddb5566
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/194740
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>
arch/arm/mach-tegra/board-dalmore-sdhci.c
arch/arm/mach-tegra/board-pluto-sdhci.c
arch/arm/mach-tegra/board-roth-sdhci.c